Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A delay locked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop (DLL) is disclosed, and includes: providing a switched capacitor stage responsive to a charge phase for charging a capacitor and a dump phase for dumping the capacitor; and aligning the charge phase and the dump phase such that a control voltage provided by the charge pump is independent of a frequency of a DLL charge and discharge phase.

Abstract: A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

Abstract: A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).

Abstract: A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

Abstract: A structure and associated method for controlling an amplitude of oscillation in a voltage controlled oscillator. The voltage controlled oscillator circuit comprises a drive circuit, an inductor/capacitor (LC) tank circuit, and a diode. The LC tank circuit and the drive circuit collectively comprise a first oscillating node and a second oscillating node. The first oscillating node is adapted to have a first voltage. The second oscillating node is adapted to have a second voltage. The first diode is adapted to control an amplitude of the first voltage and an amplitude of the second voltage.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2n−1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Abstract: A complementary metal oxide semiconductor PLL includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.

Abstract: A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2n−1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Abstract: The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2&pgr; in selectable variable phase increments of 2&pgr;/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

Abstract: A complementary metal oxide semiconductor PLL includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.

Abstract: An H-driver circuit is provided that has a mechanism for selectively reducing one or more RC time constants within the H-driver circuit. Selectively reducing one or more RC time constants within the H-driver circuit reduces the turn-ON time of one or more of the H-driver circuit's pull-up transistors, and increases the speed of the H-driver circuit with little increase in power consumption. Each RC time constant preferably is selectively reduced via a feedback path between an output terminal of the H-driver circuit and a resistance reducer operatively coupled to the pull-up transistor whose turn-ON time is to be reduced. Preferably the resistance reducer comprises a transistor, more preferably a MOSFET and most preferably a p-channel MOSFET.

Abstract: A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.