Abstract: A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Abstract: A method of interfacing between a non-continuous stream of cells of data and a continuous stream of frames of data, which includes transforming an incoming non-continuous cell stream into a continuous transmitted stream by inserting idle or non-assigned cells into the data stream during idle periods. The cells in the continuous stream are then mapped sequentially and contiguously onto the payload portions of frames. The frames are then transmitted synchronously.

Abstract: A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

Abstract: A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and outputting output clock pulses from the phase locked loop.

Abstract: A method of detecting a pulse density violation in the T1 transmission of digital signals, which includes counting bits in sets of "k" successively in n serial stages generating an empty-out signal on detection of an "empty" set of "k" bits, and generating a pulse density violation on detecting a second set of "k" zero bits in the "n" stages of bits at a time when the empty-out signal is present.

Abstract: Data to be switched is preceded by a header containing routing information for establishing a connection via a switch, and is accompanied by additional information which indicates the start of the header, in response to which a connection is established, and the end of the data, in response to which the connection is terminated. The switch is a non-saturating, non-blocking, full matrix time switch which uses the routing information to establish a connection within one tdm frame, whereby connections for data of any type (including switch control information) and of arbitrary duration can be handled efficiently. An incoming channel can be connected to any free channel or to a specified outgoing channel of any output port, and contention resolution is provided for simultaneous requests for connection to a single outgoing channel. Interconnections among crosspoint nodes are reduced and simplified using token ring and systolic interconnection techniques.