Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: A deionized-water cooling system for electrical equipment is provided. The system includes a cooling loop in which water comes into contact with the electrical equipment and a deionization bypass connected to the cooling loop. The deionization bypass includes a first filter component configured to remove dissolved oxygen, a second filter component configured to filter solid particles, a deionization cartridge configured to deionize water, and a plurality of valves configured to control a water flow within the deionization bypass.

Abstract: An IC device package includes an IC device that is connected to a lid by a thermal interface material (TIM). A catalyst material is formed upon one or more regions upon an upper surface of the IC device and/or an under surface of the lid. The catalyst material increases the rate of crosslinking of polymer chains of the TIM during TIM curing and/or increases the strength of crosslinks that link polymer chains of the TIM during TIM curing. The catalytically enhanced regions have a higher coefficient of heat transfer relative to non-catalytically enhanced regions. Therefore, the catalytically enhanced regions efficiently transfer heat from the IC device to the lid.

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Abstract: Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.

Abstract: A modified socket mechanism comprises a printed circuit board and a connector component located on a first face of the printed circuit board. The modified socket mechanism may comprise a first region of electrical contacts located on the first face. The first region of electrical contacts may be designed to interface with a processor module. The modified socket mechanism may also comprise a second region of electrical contacts located on a second face of the printed circuit board. The second region of electrical contacts may be designed to interface with a motherboard. The modified socket mechanism may also comprise a first electrical connection between the connector component and the first region of electrical contacts through the printed circuit board. Finally, the modified socket mechanism may also comprise a second electrical connection between the first region of electrical contacts and the second region of electrical contacts through the printed circuit board.

Abstract: A modified socket mechanism comprises a printed circuit board and a connector component located on a first face of the printed circuit board. The modified socket mechanism may comprise a first region of electrical contacts located on the first face. The first region of electrical contacts may be designed to interface with a processor module. The modified socket mechanism may also comprise a second region of electrical contacts located on a second face of the printed circuit board. The second region of electrical contacts may be designed to interface with a motherboard. The modified socket mechanism may also comprise a first electrical connection between the connector component and the first region of electrical contacts through the printed circuit board. Finally, the modified socket mechanism may also comprise a second electrical connection between the first region of electrical contacts and the second region of electrical contacts through the printed circuit board.

Abstract: Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.

Abstract: A deionized-water cooling system for electrical equipment is provided. The system includes a cooling loop in which water comes into contact with the electrical equipment and a deionization bypass connected to the cooling loop. The deionization bypass includes a first filter component configured to remove dissolved oxygen, a second filter component configure to filter solid particles, a deionization cartridge configured to deionize water, and a plurality of valves configured to control a water flow within the deionization bypass.