Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.

Abstract: A system, method and apparatus for aligning data sequentially received on multiple single-byte data paths are provided. A sufficient number of bytes received in each channel may be stored (e.g., buffered) and examined to properly match data from each single-byte path. Once matched, the data may be output in a proper order on the multi-byte interface, for example, via some type of multiplexor arrangement. Furthermore, alignment operations may be performed in such a way so as to reduce the latencies involved in aligning data.

Abstract: The present invention generally relates to centering a clock edge at or near the center of a data eye. Data may be sent from a first device to a second device in conjunction with a clock signal. A phase rotator operating in an external clock domain governed by the clock signal received at the second device may rotate the phase of the received clock signal to sample data. The data sampled in the unstable external clock domain may be transferred to a stable local clock domain for analysis. Feedback may be provided from the stable clock domain to the phase rotator to adjust the phase of the received clock signal to position an edge of the clock signal at or near the center of the data eye.

Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a main storage interface shared by the processors and memory cards. Each of the memory cards includes memory arrays, a hold register for retaining a data pattern stored to the arrays, a compare register and logic circuity. For a memory array diagnostic test, one of the processing devices sends a compare command (including address information) and the data pattern to one of the memory cards. In response, the logic circuity on the selected memory card stores the data pattern to its hold register and writes the data pattern into its memory arrays, then reads the data out of the memory arrays into its compare register. The contents of the compare and hold registers are compared, and an error indication provided to the processing device in the event that these registers' contents are not the same.

Abstract: A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory has a cache directory for recording main storage addresses mapped into cache memory, identifying cache lines as valid or invalid, and holding status bits of data words stored in the cache memory. According to the process, a data word is stored in the cache memory during a first clock cycle and the associated cache directory is read to determine whether the corresponding main storage address is mapped into the cache memory. If so, and if no status bits in the data word require update, the store to the cache memory is complete.

Abstract: A data processing network includes multiple processing devices, one or more memory cards in main storage, and a shared interface for processor access to main storage. Each of the memory cards includes dynamic random access memory arrays which require a periodic refresh pulse. To provide refresh pulses, each of the memory cards includes a programmable register, a counter receiving clock pulses, and a comparator. The comparator generates a request pulse each time the output from the pulse counter equals a selected value provided by the register. The register is programmable to controllably adjust the selected value, and thus select the frequency at which refresh request pulses are generated by the comparator. The memory card further includes a buffer for receiving the refresh request pulses and generating a refresh request responsive to each pulse.

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

Abstract: A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to logical addresses. The system evaluates the results of routine tests of memory and rearranges the physical addresses stored in the memory card ID register to provide an error-free portion at the desired logical address range. A separate memory configuration register stores a value representing the size of the memory cards. The value stored in the memory configuration register selects a subset of the logical memory address bits to obtain a logical card address. The logical card address selects a position in the memory card ID register to obtain the physical address of the memory card.

Abstract: Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected to the external interface between the central processing unit (CPU) and main storage and converted to a virtual address. The virtual address is compressed and entered into a large buffer via buffer control logic. The buffer control logic sends a signal to stop the CPU when the buffer becomes full and restarts it at the exact point it had stopped after the buffer has been emptied by the transfer of data from it to a slower speed storage device.