Abstract: In one embodiment, a programmable processor is adapted to include loop hardware to increase processing speed without significantly increasing power consumption. During a first pass through a loop, a first subset of a sequence of instructions may be loaded into the loop hardware. Then, during subsequent passes through the loop the first subset may be issued from the loop hardware while a second subset is retrieved from a memory device. In this manner, the second subset may be issued with no additional penalty after the first subset has been issued.

Abstract: In one embodiment, a processor is arranged to handle events. The events handled by the processor have an assigned priority. When a first event is serviced, a first priority mask is generated based on the assigned priority of the first event. The priority mask indicates a set of serviceable events and a set of non-serviceable events and may be written to a priority register. When a second event is received, the priority mask is used to determine whether the second event should preempt the first event and be immediately serviced.

Abstract: In one embodiment, a watchpoint engine generates watchpoints for code developed for a complex integrated circuit device such as a pipelined processor.

Abstract: A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.

Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.

Abstract: In one embodiment, a programmable processor is arranged to include early registers to support hardware loops. In this manner, a system may increase processing speed without significantly increasing power consumption. Loop conditions of a loop may be loaded into a set of early registers. These conditions may then be detected from the early registers before the loop conditions are written to a set of architectural registers.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register.

Abstract: In an embodiment, a system may include a processor that handles a number of events. These events may include general purpose interrupts (GPIs) assigned to particular devices in the system. Addresses for event service routines appropriate for particular events may be stored in an event vector table (EVT). In a system with a number of devices that utilize the processor's resources, some interrupts may be overloaded, that is, assigned to more than one device. If an overloaded interrupt occurs, the processor may override the EVT entry and select an address supplied by a system controller at a set of reset vector pins.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.

Abstract: A system includes a first processor, a second processor and a circuit. The first processor includes a first terminal and enters a first test mode in response to the first terminal having a first signal state. The second processor includes a second terminal. The second processor enters a second test mode in response to the second terminal having a second signal state. The circuit may regulate the timing of the first and second signal states to place both the first processor in the first test mode and the second processor in the second test mode at approximately the same time. The circuit may regulate the timing of the signals to cause the first and second processors to resume normal modes of operation at approximately the same time.

Abstract: In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.

Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.

Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.

Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register. A user program could conceivably gain access to the supervisor mode by loading the target address of an event service routine, in the supervisor instruction address space, in the LOOP_BOT register and an address in the user instruction address space in the LOOP_TOP register. If the event occurred in the supervisor mode, the program flow could branch to the address in the LOOP_TOP register, giving the user program control in the supervisor mode. To avoid this potential security hazard, the processor may disable hardware loop operations when the processor exits the user mode.