Abstract: The present invention provides a logic synthesis method and system which begins with a set of register transfer statements describing the desired logic. These statements are converted to expressions in prefix form. Next, logic reduction is performed on the individual expressions. The modified expressions are then converted to a set of logical function blocks, some of which may not be primitive blocks. Logical reduction is performed on the global set of any remaining primitives. The output of the above process is then used to synthesize the logic circuit. Included in the invention are novel techniques for performing logic reduction on the individual expressions.