Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

Abstract: An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

Abstract: An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

Abstract: Techniques and methods for reducing or preventing latch up in row decoder circuits are disclosed herein. An example apparatus may include an array of pixels, a row address decoder, and control circuitry. The row decode circuit including a plurality of decode circuits, each including at least two transistors having respective body terminals coupled to a first node. The control circuitry including a body biasing circuit coupled to the first node, the body biasing circuit to adaptively provide a bias voltage to the first node in response to an operating state of the imaging system and/or a change in one of two reference voltages based on a control signal provided by a bias control circuit.

Abstract: An example burst mode clock data recovery circuit may include a clock recovery circuit coupled to receive a plurality of data signals, and provide a recovered clock signal in response. Each of the plurality of data signals includes data and an embedded clock signal, and the plurality of data signals may be based on an encoded symbol. The clock recovery circuit is coupled to generate the recovered clock signal in response to a first one of the plurality of data signals. A data recovery circuit may be coupled to receive the plurality of data signals and the recovered clock signal, and provide a plurality of recovered data signals in response to the recovered clock signal. The data recover circuit is coupled to delay each of the plurality of data signals, and capture each of the delayed plurality of data signals in response to the at least one clock pulse.

Abstract: An interface circuit includes a pre-driver that converts the single-ended signal to an intermediate differential signal having a first voltage swing responsive to a first supply voltage supplied to the pre-driver. An output driver is coupled to receive the intermediate differential signal from the pre-driver to convert the intermediate differential signal to an output differential signal coupled to be received by a load coupled to the output driver. The output differential signal has a second voltage swing responsive to a second supply voltage supplied to the output driver. An internal regulator is coupled to receive a variable supply voltage to supply the second voltage to the output driver. The second supply voltage is generated in response to a bias signal. A replica bias circuit is coupled to receive the variable supply voltage to generate the bias signal.

Abstract: An interface circuit includes a pre-driver coupled convert a single-ended signal to an intermediate differential signal. An output driver is coupled to convert the intermediate differential signal to an output differential signal having a variable output swing responsive to a mode select signal and a second supply voltage. A replica bias circuit is coupled to receive a first supply voltage, the mode select signal, and an open termination enable signal to generate a bias signal. An internal regulator is coupled to receive the bias signal and the first supply voltage to supply the second voltage to the output driver in response to the bias signal. An open termination circuit is coupled to an output of the output driver, and is coupled to receive the open termination enable signal to couple an internal load to the output of the output driver in response to the open termination enable signal.

Abstract: A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.

Abstract: A transmitter for generating a differential signal pair including a pre-emphasis component. In an embodiment, the transmitter comprises pre-driver circuitry including an input to receive a single-ended data signal. The differential transmitter further comprises a load circuit coupled between the input and a node coupled to an output of the pre-driver circuitry which corresponds to a constituent signal of the differential signal pair. In another embodiment, the load circuit is configurable to provide a signal path between the input and the node. A configuration of the load circuit allows for a type of pre-emphasis to be included in the constituent signal.

Abstract: A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.