Abstract: A method, apparatus, and computer program product are provided for implementing global to local queue pair translation in a network transport layer. A global queue pair number is identified. The global queue pair number is translated to a smaller local queue pair number. The local queue pair number is used for storing local queue pair context data for outbound header generation and inbound header checking. Upper layers of the network protocol above the network transport layer are allowed to use the global queue pair numbers.

Abstract: A method, apparatus and computer program product are provided for implementing a transmit queue. A queue pair context memory is provided for storing a set of pointers for each queue pair. The set of pointers are used to control the transmit queue for receiving, processing, and sending messages. Responsive to identifying an error for a queue pair, a limit pointer enable bit and a limit pointer to identify a last request for processing after the error are stored in the queue pair context memory for the queue pair.

Abstract: A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation.

Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages in a system area network is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than a simple “channel semantic” transmission of a message. The use of memory semantic input/output in this way facilitates the migration of input/output adapters from a memory-mapped interface, such as Peripheral Component Interconnect (PCI), to a system area network.

Abstract: An apparatus and method for an advanced multiplexing technique to allow a single host to support multiple Internet Protocol (IP) queue pairs with little or no overhead are provided. With the apparatus and method, after a queue pair is created, Internet Protocol filter attributes and values are set up for the queue pair through value added features to the standard InfiniBand “QP Modify” method. The IP filters are used during normal operations to determine which queue pair is associated with an incoming packet. During normal operations, when a channel adapter receives an Internet Protocol (IP) over InfiniBand (IB) packet, it uses one or more of several fields in the packet's transport and/or network header to determine which queue pair shall receive the packet. Thus, the host channel adapter uses the IP filters to route incoming packets to the appropriate queue pair and thereby allow more than one queue pair to be used to support IP.

Abstract: A mechanism for initiating and completing one or more I/O transactions using channel and memory semantic messages is disclosed. Channel semantic messages are messages that are simply packetized and transmitted. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.

Abstract: An apparatus and method for an advanced tunneling technique to allow Internet Protocol (IP) frames to be routed through System Area Network (SAN) components with little or no overhead are provided. Furthermore, an apparatus and method for processing Internet Protocol (IP) version 6 datagrams over a SAN using basic raw and unreliable datagram (RawD and UD respectively) interfaces are provided. The apparatus and method allows a host channel adapter (HCA) to attach directly to an IP router which supports multiple link protocols, for example a router than attaches InfiniBand (IB) links and Ethernet links, and uses IP as the networking protocol on both. In this way, a SAN may be coupled to a LAN via a router with minimal hardware and overhead.

Abstract: An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.

Abstract: A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

Abstract: An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

Abstract: A method, device and system for configuring multifunction I/O device adapters connected to a bus utilizes a slot owner configuration register to identify the ownership of each function slot within the multi-function I/O device adapter. An intelligent I/O device adapter or controller within the multi-function I/O device adapter may control other I/O adapters located in other function slots through the information provided in the slot owner configuration register. Ownership of each slot is initially set, upon power up, to the host unit or processor complex. Thereafter, each intelligent I/O device adapter or controller determines the presence of adapters at other function slots to be controlled, and records this information in the slot owner configuration register.

Abstract: An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count.

Abstract: An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state.

Abstract: An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

Abstract: An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.