Patents by Inventor Charles See Yeung Kwong
Charles See Yeung Kwong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11994945Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device. The operations performed by the processing device further include determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.Type: GrantFiled: April 6, 2023Date of Patent: May 28, 2024Assignee: Micron Technology, Inc.Inventors: Zhenming Zhou, Tingjun Xie, Charles See Yeung Kwong
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Patent number: 11989107Abstract: A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.Type: GrantFiled: July 8, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Charles See Yeung Kwong
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Publication number: 20240145010Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
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Patent number: 11914510Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.Type: GrantFiled: May 4, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Mikai Chen, Zhengang Chen, Charles See Yeung Kwong
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Publication number: 20240062839Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Inventors: Wei Wang, Seungjune Jeon, Yang Liu, Charles See Yeung Kwong
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Patent number: 11901014Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: GrantFiled: May 9, 2022Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
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Publication number: 20240045595Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: Li-Te Chang, Murong Lang, Charles See Yeung Kwong, Vamsi Pavan Rayaprolu, Seungjune Jeon, Zhenming Zhou
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Publication number: 20230402108Abstract: It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.Type: ApplicationFiled: August 28, 2023Publication date: December 14, 2023Inventors: Tingjun Xie, Zhenming Zhou, Zhenlei Shen, Charles See Yeung Kwong
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Publication number: 20230393920Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.Type: ApplicationFiled: July 6, 2022Publication date: December 7, 2023Inventors: Charles See Yeung Kwong, Seungjune Jeon, Wei Wang, Zhenming Zhou
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Publication number: 20230360704Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
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Patent number: 11790998Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.Type: GrantFiled: August 25, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Zhenming Zhou, Zhenlei Shen, Charles See Yeung Kwong
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Patent number: 11756604Abstract: A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.Type: GrantFiled: September 16, 2022Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Charles See Yeung Kwong, Seungjune Jeon
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Publication number: 20230244566Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device. The operations performed by the processing device further include determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Zhenming Zhou, Tingjun Xie, Charles See Yeung Kwong
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Patent number: 11694017Abstract: A quality rating for a memory device to be installed at a memory sub-system is determined, where the quality rating corresponds to a performance of the memory device at one or more operating temperatures. A determination is made whether the quality rating for the memory device satisfies a first quality rating condition associated with a first temperature zone of two or more temperature zones of the memory sub-system. Responsive to the determination that the quality rating for the memory device satisfies the first quality rating condition, the memory device is assigned to be installed at a first memory device socket of the first temperature zone.Type: GrantFiled: July 15, 2020Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Zhenlei Shen, Tingjun Xie, Charles See Yeung Kwong
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Patent number: 11656936Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit.Type: GrantFiled: September 7, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Zhenming Zhou, Tingjun Xie, Charles See Yeung Kwong
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Patent number: 11615830Abstract: A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.Type: GrantFiled: June 4, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Seungjune Jeon, Zhengang Chen, Zhenlei Shen, Charles See Yeung Kwong
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Publication number: 20230074538Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Zhenming Zhou, Tingjun Xie, Charles See Yeung Kwong
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Publication number: 20230067639Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Tingjun Xie, Zhenming Zhou, Zhenlei Shen, Charles See Yeung Kwong
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Publication number: 20230051408Abstract: A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.Type: ApplicationFiled: September 16, 2022Publication date: February 16, 2023Inventors: Charles See Yeung Kwong, Seungjune Jeon
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Patent number: 11495279Abstract: A write operation performed on a first memory unit of a memory device is detected, wherein the first memory unit comprises one or more memory cells. Responsive to detecting the write operation, a value of a counter associated with the first memory unit is incremented. It is determined whether the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range. Responsive to determining that the value of the counter satisfies the threshold criterion, a refresh operation is performed on a second memory unit.Type: GrantFiled: August 16, 2021Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: Charles See Yeung Kwong, Seungjune Jeon