Abstract: A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM and other hybrid modulations. The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyzer (ORA). The multiplier extracts the spectrum information at the desired frequency without using Fast Fourier Transform (FFT) and the accumulator picks up the DC component by averaging the multiplier output.

Abstract: Systems and methods for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach are described. In one method according to the present invention, two or more paths under test receive a test pattern approximately simultaneously. The two paths are substantially identical and thus should propagate the signal in approximately the same amount of time. An output response analyzer receives the signal from each of the paths and determines the interval between them. The output response analyzer next determines whether a delay fault has occurred based at least in part on the interval. In one embodiment, the output response analyzer comprises an oscillator and a counter.