Abstract: A signal processing system that includes a ring bus; a multiplicity of system modules, each coupled to the ring bus and operative to receive and transfer blocks of data words over the ring bus; and a bus control module coupled to the ring bus and operative to support simultaneous data transfers between specified pairs of system modules in accordance with concurrent execution of multiple programs of data transfer instructions. In an alternate embodiment, the signal processing system may include a plurality of ring buses wherein each system module is coupled to all of the ring buses and operative to receive and transfer blocks of data words over any one of the ring buses. In addition, the bus control module is also coupled to all of the ring buses and operative to support simultaneous data transfers between specified pairs of system modules over all of the ring buses. Moreover, each ring bus may comprise individual bus segments for system module to system module coupling about the ring.

Abstract: A digital signal processing system and more especially a programmable bulk memory included therein comprising a plurality of memory sections independently controlled and simultaneously operative for transferring blocks or vectors of digital data words directly between selected memory sections and external data handling units while maintaining the corresponding variety of data handling throughput rates thereof without the need for input-output buffer type memories coupled therebetween is disclosed. A method of addressing the sections of addressable memory locations for accessing therefrom and storing therein blocks of data words in accordance with predetermined sequences is also disclosed.