Patents by Inventor Charles W. T. Longway

Charles W. T. Longway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiport memory and method
    Patent number: 5586072
    Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: December 17, 1996
    Assignee: Harris Corporation
    Inventors: Charles W. T. Longway, William R. Young
  • Multiport memory and method
    Patent number: 5563834
    Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: October 8, 1996
    Assignee: Harris Corporation
    Inventors: Charles W. T. Longway, William R. Young
  • Rom cell for a multiport memory and method
    Patent number: 5544095
    Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: August 6, 1996
    Assignee: Harris Corporation
    Inventors: Charles W. T. Longway, William R. Young
  • Semiconductor ROM device and method
    Patent number: 5440506
    Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: August 8, 1995
    Assignee: Harris Corporation
    Inventors: Charles W. T. Longway, William R. Young
  • Flash-clear of ram array using partial reset mechanism
    Patent number: 5373466
    Abstract: A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional `resetable` memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be output as all zeros.
    Type: Grant
    Filed: March 25, 1992
    Date of Patent: December 13, 1994
    Assignee: Harris Corporation
    Inventors: David S. Landeta, William R. Young, Charles W. T. Longway