Abstract: The specification describes a thin film Integrated Passive Device (IPD) design that achieves isolation between conductive runners by shielding the top and bottom regions of a noisy runner with metal shield plates. The shield plates are derived from metal interconnect layers. The invention can be implemented by merely modifying the mask pattern for the metal interconnect layers. No added elements or steps are needed to fabricate the IPDs. The invention is suitable for use in Multi-Chip Modules (MCMs) or other arrangements where digital circuits and RF circuits are in close proximity.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a silicon substrate covered with an oxide layer. Unwanted accumulated charge at the silicon/oxide interface are rendered immobile by creating trapping centers in the silicon surface. The trapping centers are produced by a polysilicon layer interposed between the silicon substrate and the oxide layer.

Abstract: The specification describes a thin film Integrated Passive Device (IPD) design that achieves isolation between conductive runners by shielding the top and bottom regions of a noisy runner with metal shielding plates. The shielding plates are derived from metal interconnect layers. The invention can be implemented by merely modifying the mask pattern for the metal interconnect layers. No added elements or steps are needed to fabricate the IPDs. The invention is suitable for use in Multi-Chip Modules (MCMs) or other arrangements where digital circuits and RF circuits are in close proximity.

Abstract: The specification describes an integrated passive device (IPD) designed to allow implementation of cellular RF and Wi-Fi RF in a single hand held device. To address the problem of RF interference a thin film RF high rejection bandpass filter is formed in an IPD implementation. The IPD implementation preferably uses silicon as the substrate material. This allows the thin film RF high rejection bandpass filter to be made using silicon processing technology, and thus produce low cost filters that still meet stringent performance requirements demanded due to the co-existing RF units. In preferred embodiments of the invention, wafer level processing using silicon substrates adds to the cost effective manufacture of the highly functional IPDs.

Abstract: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are dis-integrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices for the impedance matching networks are built into the high resistivity SIIS using thin-film technology.

Abstract: The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.

Abstract: The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.