Patents by Inventor Charlie J. Hewett

Charlie J. Hewett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9626274
    Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett
  • Patent number: 9465680
    Abstract: A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: October 11, 2016
    Assignee: INTEL CORPORATION
    Inventors: Michael W. Chynoweth, Jonathan D. Combs, Angela D. Schmid, Kimberly C. Weier, Ahmad Yasin, Jason W. Brandt, Charlie J. Hewett, Seth Abraham, Matthew C. Merten
  • Publication number: 20160179650
    Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett