Abstract: A computer program synchronization instruction is employed to synchronize multiple processing devices sharing main storage through a common interface. The processors execute the synchronization instruction in turn, and all except the final processor are forced into a temporary holdoff condition and execute no further computer program instructions. The final processor to execute the synchronization program becomes a master, releasing itself and the "slave" devices simultaneously to resume executing instructions. In order to force contentions between processors, a selected delay may be entered into the instruction stream of at least one of the processing devices. The delay can be incremented each time the synchronization instruction is executed, if desired. The forced contentions permit a testing of various serialization mechanisms designed to resolve contentions.

Abstract: In connection with an information processing network in which multiple processing devices have individual cache memories and also share a main storage memory, a process is disclosed for allocating multiple data operations or tasks for subsequent execution by the processing devices. A plurality of task dispatching elements (TDE) forming a task dispatching queue are scanned in an order of descending priority, for either a specific affinity to a selected one of the processing devices, or a general affinity to all of the processing devices. TDEs with specific affinity are assigned immediately if the selected processor is available, while TDEs of general affinity are reserved. TDEs with a specific affinity are bypassed if the selected processor is not available, or reserved if a predetermined bypass threshold has been reached. Following the primary scan a secondary scan, in an order of ascending priority, assigns any reserved tasks to the processing devices still available, without regard to processor affinity.