Patents by Inventor Charlotte D Adams
Charlotte D Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10755918Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.Type: GrantFiled: November 16, 2018Date of Patent: August 25, 2020Assignee: GLOBALFOUNDRIES, INC.Inventors: Man Gu, Tao Han, Charlotte D. Adams
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Publication number: 20200161122Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Man GU, Tao HAN, Charlotte D. ADAMS
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Patent number: 9087722Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: GrantFiled: November 14, 2014Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Charlotte D. Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Publication number: 20150069525Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Charlotte D. Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Patent number: 8030709Abstract: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.Type: GrantFiled: December 12, 2007Date of Patent: October 4, 2011Assignees: International Business Machines Corporation, Globalfoundries, Inc.Inventors: Charlotte D. Adams, Bruce B. Doris, Philip Fisher, William K. Henson, Jeffrey W. Sleight
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Publication number: 20090179283Abstract: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.Type: ApplicationFiled: December 12, 2007Publication date: July 16, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC. (AMD)Inventors: Charlotte D. Adams, Bruce B. Doris, Philip Fisher, William K. Henson, Jeffrey W. Sleight
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Patent number: 7230336Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.Type: GrantFiled: January 7, 2003Date of Patent: June 12, 2007Assignee: International Business Machines CorporationInventors: Charlotte D Adams, Anthony K. Stamper
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Publication number: 20030232494Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.Type: ApplicationFiled: January 7, 2003Publication date: December 18, 2003Inventors: Charlotte D. Adams, Anthony K. Stamper
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Patent number: 6566242Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.Type: GrantFiled: March 23, 2001Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: Charlotte D. Adams, Anthony K. Stamper