Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

Abstract: A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, wherein the first top surface has a first insulating layer formed thereon, and the sensing chip comprises a sensing device adjacent to the first top surface and a plurality of conductive pads formed within the first insulating and adjacent to the sensing device, and a wiring layer formed on the first bottom surface to respectively connect to each of the conductive pads; and a dam formed on the first insulating layer adjacent to the sensing device.

Abstract: The bio-expression system comprising: a process system used to process data and a three-dimension image generating module embedded in the computing system, wherein while input of a set of two-dimensional individual model sections is fed into the process system, the three-dimension image generating module is responsive to the input of the two-dimension individual model sections and is capable of processing an individual model construction and model-averaging procedure, thereby generating an average model for each individual dataset. A database includes a bio-expression sub-database, cellular network sub-database and fine structure sub-database, wherein the database is coupled to the process system to store at least the average model. A stereoscopic projecting system is coupled to the process system to display stereoscopic images for active or passive virtual reality applications, thereby presenting the bio-expressions, cellular networks or bio-fine structures under the input instruction of the process system.

Abstract: The bio-expression system comprising: a process system used to process data and a three-dimension image generating module embedded in the computing system, wherein while input of a set of two-dimensional individual model sections is fed into the process system, the three-dimension image generating module is responsive to the input of the two-dimension individual model sections and is capable of processing an individual model construction and model-averaging procedure, thereby generating an average model for each individual dataset. A database includes a bio-expression sub-database, cellular network sub-database and fine structure sub-database, wherein the database is coupled to the process system to store at least the average model. A stereoscopic projecting system is coupled to the process system to display stereoscopic images for active or passive virtual reality applications, thereby presenting the bio-expressions, cellular networks or bio-fine structures under the input instruction of the process system.

Abstract: An inductively-coupled plasma etch apparatus and a feedback control method thereof are provided. A voltage/current measuring device is connected to an electrostatic chuck of the plasma etching apparatus, so as to measure the RF current, voltage and the phase angle between them on the electrostatic chuck. The ion current and the RF bias voltage are obtained by calculation of the RF current, voltage and the phase angle. Finally, using the obtained ion current and the RF bias voltage to feedback control the RF power generator in order to achieve the desired plasma status.

Abstract: There is provided a process and its system for fabricating plasma with feedback control on plasma density. This process uses a heterodyne millimeter wave interferometer as a sensor to measure the plasma density in the process container and the plasma density that is needed in the plasma fabricating process, and then provides real-time information of the measurements to a digital control device which makes numerical calculations and then drives the RF power generator to change the RF output power so as to enable the plasma density in the plasma fabricating process to be close to the expected plasma density. The conventional operation parameter method is to control air pressure, RF power, gas flow quantity, temperature and so on. However, it does not control the plasma parameter that has the most direct influence on the process. Therefore, this method cannot guarantee that, in the process of fabricating wafers, different batches of wafers will be operated under similar process plasma conditions.