Patents by Inventor Che-An Yao
Che-An Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240177319Abstract: Many unsupervised domain adaptation (UDA) methods have been proposed to bridge the domain gap by utilizing domain invariant information. Most approaches have chosen depth as such information and achieved remarkable successes. Despite their effectiveness, using depth as domain invariant information in UDA tasks may lead to multiple issues, such as excessively high extraction costs and difficulties in achieving a reliable prediction quality. As a result, we introduce Edge Learning based Domain Adaptation (ELDA), a framework which incorporates edge information into its training process to serve as a type of domain invariant information. Our experiments quantitatively and qualitatively demonstrate that the incorporation of edge information is indeed beneficial and effective, and enables ELDA to outperform the contemporary state-of-the-art methods on two commonly adopted benchmarks for semantic segmentation based UDA tasks.Type: ApplicationFiled: November 24, 2023Publication date: May 30, 2024Applicant: MEDIATEK INC.Inventors: Ting-Hsuan Liao, Huang-Ru Liao, Shan-Ya Yang, Jie-En Yao, Li-Yuan Tsao, Hsu-Shen Liu, Bo-Wun Cheng, Chen-Hao Chao, Chia-Che Chang, Yi-Chen Lo, Chun-Yi Lee
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Publication number: 20240177269Abstract: A method of local implicit normalizing flow for arbitrary-scale image super-resolution, an associated apparatus and an associated computer-readable medium are provided. The method applicable to a processing circuit may include: utilizing the processing circuit to run a local implicit normalizing flow framework to start performing arbitrary-scale image super-resolution with a trained model of the local implicit normalizing flow framework according to at least one input image, for generating at least one output image, where a selected scale of the output image with respect to the input image is an arbitrary-scale; and during performing the arbitrary-scale image super-resolution with the trained model, performing prediction processing to obtain multiple super-resolution predictions for different locations of a predetermined space in a situation where a same non-super-resolution input image among the at least one input image is given, in order to generate the at least one output image.Type: ApplicationFiled: November 24, 2023Publication date: May 30, 2024Applicant: MEDIATEK INC.Inventors: Jie-En Yao, Yi-Chen Lo, Li-Yuan Tsao, Shou-Yao Tseng, Chia-Che Chang, Chun-Yi Lee
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Patent number: 11990418Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.Type: GrantFiled: August 27, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hua Wang, Po-Chen Lai, Ping-Tai Chen, Che-Chia Yang, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11978722Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Po-Chen Lai, Che-Chia Yang, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240120313Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
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Publication number: 20240113345Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.Type: ApplicationFiled: May 23, 2023Publication date: April 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
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Publication number: 20240096822Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
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Publication number: 20240088061Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Patent number: 11733746Abstract: An example apparatus to retain a computer power brick in a power brick holder includes a plate and a positioning mechanism removably attached at any of a plurality of positions on the plate. The positioning mechanism is attached at a preset position on the plate based on a size of the power brick.Type: GrantFiled: July 24, 2019Date of Patent: August 22, 2023Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chin-Chang Ho, Hung-Ming Lin, Hong-Tao Hsieh, Che-An Yao
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Publication number: 20230043887Abstract: Compositions for use as a vaccine against SARS-CoV-2 infection are disclosed, which comprise either a polypeptide that comprises at least one surge-associated mutation (e.g., deletion) in its amino acid sequence or a nucleic acid (e.g., mRNA) that encodes said polypeptide. Also disclosed are formulations that include these compositions, antibodies or their antigen-biding fragments directed to these polypeptides, methods of making such antibodies, methods of vaccinating subjects against SARS-CoV-2 infection, and methods of selecting an antibody, convalescent plasma, or vaccine against SARS-CoV-2 infection.Type: ApplicationFiled: May 23, 2022Publication date: February 9, 2023Inventors: Venkataramanan Soundararajan, Aiveliagaram Venkatakrishnan, Joseph Du-Che Yao
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Publication number: 20220397946Abstract: An example ventilation system for a computing device includes: a cover slidably engageable with a housing of the computing device to a closed position defining an internal space of the computing device, the cover having first ventilation holes; a system mesh slidably engaged with the cover, the system mesh having second ventilation holes; and a stopper disposed in the internal space of the computing device, the stopper to stop the system mesh at a predefined position when the cover is engaged with the housing in the closed position, wherein the first ventilation holes and the second ventilation holes overlap to define system ventilation holes for the computing device.Type: ApplicationFiled: October 31, 2019Publication date: December 15, 2022Applicant: Hewlett-Packard Development Company, L.P.Inventors: Chin-Chang Ho, Hung-Ming Lin, Lan-Chin Chiou, Wei-Chih Tsao, Che-An Yao
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Publication number: 20220271061Abstract: The present disclosure discloses a manufacturing method of a pixel structure of a reflective display comprising: providing a substrate; forming a shielding layer on the substrate; forming a low reflective layer on the shielding layer; and forming a reflective layer on the low reflective layer, wherein the reflective layer comprises a plurality of reflection regions, the plurality of reflection regions are arranged at intervals, and a part of the low reflective layer is exposed between the plurality of reflection regions. In the present disclosure, the reflection of light in the gap between the pixels is avoided by the low reflective layer, such that the notice of liquid crystal disturbance by human eyes is reduced, and a reflective display with good display function and low power consumption is implemented.Type: ApplicationFiled: May 13, 2022Publication date: August 25, 2022Applicant: GIANTPLUS TECHNOLOGY CO., LTD.Inventors: I-Ta JIANG, Che-Yao WU, Kai-Ju CHOU
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Publication number: 20220179464Abstract: An example apparatus to retain a computer power brick in a power brick holder includes a plate and a positioning mechanism removably attached at any of a plurality of positions on the plate. The positioning mechanism is attached at a preset position on the plate based on a size of the power brick.Type: ApplicationFiled: July 24, 2019Publication date: June 9, 2022Applicant: Hewlett-Packard Development Company, L.P.Inventors: Chin-Chang Ho, Hung-Ming Lin, Hong-Tao Hsieh, Che-An Yao
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Publication number: 20220102386Abstract: The present disclosure discloses a pixel structure of a reflective display comprising a substrate, a shielding layer, a low reflective layer, and a reflective layer. The shielding layer is disposed on the substrate. The low reflective layer is disposed on the shielding layer. The reflective layer is disposed on the low reflective layer, wherein the reflective layer comprises a plurality of reflection regions, the plurality of reflection regions are arranged at intervals. A part of the low reflective layer is exposed between the plurality of reflection regions. In the present disclosure, the reflection of light in the gap between the pixels is avoided by the low reflective layer, such that the notice of liquid crystal disturbance by human eyes is reduced, and a reflective display with good display function and low power consumption is implemented.Type: ApplicationFiled: October 29, 2020Publication date: March 31, 2022Applicant: GIANTPLUS TECHNOLOGY CO., LTD.Inventors: I-Ta JIANG, Che-Yao WU, Kai-Ju CHOU
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Publication number: 20220085075Abstract: A display panel including a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer is provided. The first metal layer is disposed on the substrate and includes a first storage electrode. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed on the first insulating layer and includes a second storage electrode. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer and includes a third storage electrode. A first storage capacitance is constituted by the first and second storage electrode as well as the first insulating layer located between thereof, and a second storage capacitance is constituted by the second and third storage electrode as well as the second insulating layer located between thereof.Type: ApplicationFiled: October 19, 2020Publication date: March 17, 2022Applicant: GIANTPLUS TECHNOLOGY CO., LTDInventors: Che-Yao Wu, Kai-Ju Chou, I-Ta Jiang
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Patent number: 11256131Abstract: The present disclosure discloses a jump connection structure of a reflective display comprising a substrate, a shielding layer, a low reflective layer, an organic layer, a first transparent conductive layer, and a first reflective layer. The shielding layer is disposed on the substrate. The low reflective layer is disposed on the shielding layer. The organic layer is disposed on the low reflective layer, wherein the organic layer and the low reflective layer have a first via, and a part of the shielding layer is exposed from the first via. The first transparent conductive layer is disposed on the exposed shielding layer. The first reflective layer is disposed on a top surface of the organic layer, a side surface of the organic layer, and the first transparent conductive layer. In the present disclosure, a reflective display with good display function and low power consumption is implemented by the jump connection structure.Type: GrantFiled: October 29, 2020Date of Patent: February 22, 2022Assignee: GIANTPLUS TECHNOLOGY CO., LTD.Inventors: I-Ta Jiang, Che-Yao Wu, Kai-Ju Chou
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Patent number: 11215870Abstract: A pixel structure having a first gray scale display region and a second gray scale display region is provided. The first and the second gray scale display region respectively comprises two first display blocks and a second display block located therebetween. The pixel structure comprises first conductive electrodes, a second conductive electrode, a first active component and a second active component. The first conductive electrodes respectively disposed in the two first display blocks of the first gray scale display region are connected. The second conductive electrode is disposed in the second gray scale display region. The first active component is electrically connected to the first conductive electrodes by a first contact window located at one of the two first display blocks. The second active component is electrically connected to the second conductive electrode by a second contact window located at the second display block.Type: GrantFiled: October 15, 2020Date of Patent: January 4, 2022Assignee: GIANTPLUS TECHNOLOGY CO., LTDInventors: I-Ta Jiang, Che-Yao Wu
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Patent number: 11177405Abstract: A thin film solar cell including a substrate, an insulating layer, a first electrode layer, a photovoltaic conversion layer and a second electrode layer is provided. The insulating layer is disposed on the substrate and includes a plurality of microstructures. An orthographic projection of the plurality of microstructures is a regular geometric shape or an irregular geometric shape regarding to a normal direction of the substrate. The first electrode layer is disposed on the insulating layer. A thickness of the first electrode layer is less than 1 ?m or is equal to 1 ?m. The photovoltaic conversion layer is disposed on the first electrode layer. The second electrode layer is disposed on the photovoltaic conversion layer.Type: GrantFiled: December 5, 2019Date of Patent: November 16, 2021Assignee: GIANTPLUS TECHNOLOGY CO., LTDInventor: Che-Yao Wu
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Patent number: 11150530Abstract: A manufacturing method of a display panel including following steps is provided. Providing a substrate. Forming a first metal layer including a first storage electrode on the substrate. Forming a first insulating layer on the first metal layer. Forming a second metal layer including a second storage electrode on the first insulating layer. Forming a second insulating layer on the second metal layer. Forming a third metal layer including a third storage electrode on the second insulating layer. A first storage capacitance is constituted by the first storage electrode and the second storage electrode as well as the first insulating layer located between the first storage electrode and the second storage electrode, and a second storage capacitance is constituted by the second storage electrode and the third storage electrode as well as the second insulating layer located between the second storage electrode and the third storage electrode.Type: GrantFiled: October 19, 2020Date of Patent: October 19, 2021Assignee: GIANTPLUS TECHNOLOGY CO., LTDInventors: Che-Yao Wu, Kai-Ju Chou, I-Ta Jiang