Patents by Inventor Che-Hao Tu
Che-Hao Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951587Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.Type: GrantFiled: August 12, 2019Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
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Publication number: 20240105460Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20240050995Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.Type: ApplicationFiled: August 15, 2022Publication date: February 15, 2024Inventors: Chih-Wen Liu, Yeo-Sin Lin, Shu-Wei Hsu, Che-Hao Tu, Hui-Chi Huang, Kei-Wei Chen
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Patent number: 11854821Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: April 1, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20210225657Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: April 1, 2021Publication date: July 22, 2021Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20210166972Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Inventors: Che-Liang CHUNG, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
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Patent number: 10971370Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: December 16, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 10943822Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.Type: GrantFiled: March 15, 2018Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
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Publication number: 20210023678Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
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Patent number: 10800004Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: GrantFiled: January 18, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
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Publication number: 20200118827Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20200101582Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: ApplicationFiled: January 18, 2019Publication date: April 2, 2020Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
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Publication number: 20200094369Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.Type: ApplicationFiled: August 12, 2019Publication date: March 26, 2020Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
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Patent number: 10510552Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: April 20, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20190287852Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Che-Liang Chung, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
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Publication number: 20180240679Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9960050Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: August 5, 2013Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9941109Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: GrantFiled: June 29, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9922837Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.Type: GrantFiled: March 2, 2016Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20180005840Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen