Patents by Inventor Che-Nan Tsai

Che-Nan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and fabrication method thereof
    Patent number: 9000568
    Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
  • Manufacturing method for semiconductor device having metal gate
    Patent number: 8551876
    Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
  • SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20130075874
    Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 28, 2013
    Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
  • MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE
    Publication number: 20130045594
    Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
  • SEMICONDUCTOR PROCESS
    Publication number: 20130012012
    Abstract: A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.
    Type: Application
    Filed: July 10, 2011
    Publication date: January 10, 2013
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Shao-Wei Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
  • SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF
    Publication number: 20120306028
    Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.
    Type: Application
    Filed: May 30, 2011
    Publication date: December 6, 2012
    Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Chien-Liang Lin, Shao-Wei Wang, Ying-Wei Yen