Patents by Inventor Che-Pin Tseng

Che-Pin Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990111
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Sheng-Pin Su, Yuan-I Tseng, Che-Hung Lai, Chien-Yi Wang, Chuan-Te Chang
  • Patent number: 5837426
    Abstract: A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: November 17, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Che-Pin Tseng, Wei-Jiang Lin, Wen-Cheng Tien, Yun-Kuei Yang
  • Patent number: 5830772
    Abstract: Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: November 3, 1998
    Assignee: United MicroelectronicsCorp.
    Inventors: Che-Pin Tseng, Nai-Jen Yeh, Yu-Chih Chuang, Cheng-Chih Kung