Patents by Inventor Che-Yuan Sun
Che-Yuan Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11119416Abstract: A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.Type: GrantFiled: June 12, 2019Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Yuan Sun, Yen-Liang Chen, He Fan, Yen-Hung Chen, Kai Lin
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Patent number: 10867116Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: December 18, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20200125785Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20200057388Abstract: A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.Type: ApplicationFiled: June 12, 2019Publication date: February 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Yuan SUN, Yen-Liang CHEN, He FAN, Yen-Hung CHEN, Kai LIN
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Patent number: 10521548Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: July 23, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Patent number: 10163733Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.Type: GrantFiled: May 31, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Rui Hu, Shu-Chuan Chuang, Che-Yuan Sun, Chih-Ming Ke
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Publication number: 20180330040Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: July 23, 2018Publication date: November 15, 2018Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Patent number: 10031997Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: December 21, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20180196911Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: December 21, 2016Publication date: July 12, 2018Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20170345725Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: Jia-Rui HU, Shu-Chuan CHUANG, Che-Yuan SUN, Chih-Ming KE
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Patent number: 9132263Abstract: A flexible ultrasound actuator is provided. The flexible ultrasound actuator includes a fixing element and a piezoelectric film structure. At least two ends of the piezoelectric film structure are fixed on the fixing element. The piezoelectric film structure comprises at least two curvatures.Type: GrantFiled: December 28, 2012Date of Patent: September 15, 2015Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Ching Ko, Che-Yuan Sun, Chang-Yi Chen
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Patent number: 8588438Abstract: A driving interface device adaptive to a flat speaker is introduced herein. The driving interface device is coupled with an external sound source for receiving sound signals, and boosts voltage levels of the sound signals to drive the thin flat speaker without using an external power source. In one embodiment, an impedance component is provided in the driving interface device for coupling to the external sound source, so as to drive the flat speaker.Type: GrantFiled: December 30, 2010Date of Patent: November 19, 2013Assignee: Industrial Technology Research InstituteInventors: Kuo-Hua Tseng, Chang-Ho Liou, Ming-Daw Chen, Kuan-Wei Chen, Che-Yuan Sun
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Publication number: 20120106761Abstract: A driving interface device adaptive to a flat speaker is introduced herein. The driving interface device is coupled with an external sound source for receiving sound signals, and boosts voltage levels of the sound signals to drive the thin flat speaker without using an external power source. In one embodiment, an impedance component is provided in the driving interface device for coupling to the external sound source, so as to drive the flat speaker.Type: ApplicationFiled: December 30, 2010Publication date: May 3, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Hua Tseng, Chang-Ho Liou, Ming-Daw Chen, Kuan-Wei Chen, Che-Yuan Sun
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Publication number: 20120051564Abstract: A reliable flat speaker structure and a manufacturing method thereof are introduced herein. The flat speaker structure includes a first and a second vapor-resistant structure and a flat speaker unit structure. The first and second vapor-resistant structures are respectively disposed on an outer side of the flat speaker structure or an outer side of the vibrating membrane, by which the vapor in the environment is prevented from entering the inner space of the flat speaker structure. The flat speaker unit structure at least includes a first porous electrode, an electret layer with a metal film, and a second porous electrode. Signal sources in an AC form may be applied to the first and second porous electrodes and/or the metal film of the electret layer and respective sounds are generated from the flat speaker structure by attractive or repulsive forces between the porous electrodes and the electret layer.Type: ApplicationFiled: August 31, 2011Publication date: March 1, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chang-Ho Liou, Ming-Daw Chen, Kuo-Hua Tseng, Kuan-Wei Chen, Che-Yuan Sun