Patents by Inventor Chee Hu

Chee Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor with dedicated virtual functions and dynamic assignment of functional resources
    Patent number: 9128769
    Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 8, 2015
    Assignee: Cavium, Inc.
    Inventors: Jeffrey Schroeder, Jeff Pangborn, Najeeb Ansari, Bryan Chin, Leo Chen, Ahmed Shahid, Paul Scrobohaci, Chee Hu, Michael Carns, Wu Ye, Brian Hunter
  • PROCESSOR WITH DEDICATED VIRTUAL FUNCTIONS AND DYNAMIC ASSIGNMENT OF FUNCTIONAL RESOURCES
    Publication number: 20130097598
    Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: Cavium, Inc.
    Inventors: Jeffrey Schroeder, Jeff Pangborn, Najeeb Ansari, Bryan Chin, Leo Chen, Ahmed Shahid, Paul Scrobohaci, Chee Hu, Michael Carns, Wu Ye, Brian Hunter
  • Apparatus for high speed communication system
    Patent number: 6449274
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 10, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Holden, Brian D. Alleyne, Darren S. Braun, Imran Chaudhri, Kevin Reno, Nadeem Haq, Chee Hu, Raghavan P Menon, Steve T Sprouse, Dinesh Venkatachalam
  • Method for a high speed communication system
    Patent number: 6445705
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 3, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Holden, Brian D. Alleyne, Darren S. Braun, Nadeem Haq, Chee Hu
  • Method and apparatus for high speed, scalable communication system
    Patent number: 6188690
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 13, 2001
    Assignee: PMC-Sierra, Inc.
    Inventors: Brain D. Holden, Brian D. Alleyne, Darren S. Braun, Kevin Reno, Chee Hu, Raghavan Menon, Steve Sprouse