Patents by Inventor Chee Kay CHOW
Chee Kay CHOW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136217Abstract: A manufacturing system includes a substrate disposed on a conveyer system. The conveyer system includes a pair of side supports. The substrate is moved on the conveyer system until the substrate is disposed over a bottom support block. The bottom support block is raised to physically contact the substrate. A transfer arm module is provided. The transfer arm module includes a flat bottom surface and an opening formed in the flat bottom surface. The transfer arm module is disposed with the flat bottom surface physically contacting the substrate opposite the bottom support block. A vacuum is enabled through the opening of the transfer arm module. The substrate is lifted off the bottom support block using the vacuum. The substrate is moved over a printing pallet using the transfer arm module. The vacuum is disabled when the substrate is in a positioning area of the printing pallet.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Applicant: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Chee Kay Chow, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Wing Keung Lam
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Publication number: 20240055292Abstract: A first carrier has a first plate. A tape is disposed on the first plate. A second plate is disposed over the first plate. The second plate has a trench aligned to the tape and an opening formed through the second plate over the tape. A singulated semiconductor package is disposed on the tape in the opening of the second plate. A second carrier has a static datum and a movable datum. The movable datum is moved toward the static datum. An aperture substrate is disposed around the static datum and movable datum. A manufacturing process is performed on the aperture substrate.Type: ApplicationFiled: August 11, 2023Publication date: February 15, 2024Applicant: UTAC Headquarters Pte. Ltd.Inventors: Roel Adeva Robles, Chee Kay Chow
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Publication number: 20220331917Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A method for forming the wafer adaptor ring assembly is also disclosed.Type: ApplicationFiled: April 18, 2022Publication date: October 20, 2022Inventors: Enrique Sarile, JR., Chee Kay Chow, Dzafir Bin Mohd Shariff
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Publication number: 20220336283Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A system for assembling and disassembling the wafer adaptor ring assembly is also disclosed.Type: ApplicationFiled: April 18, 2022Publication date: October 20, 2022Inventors: Enrique Jr Sarile, Chee Kay Chow, Dzafir Bin Mohd Shariff
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Patent number: 11177301Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.Type: GrantFiled: November 18, 2019Date of Patent: November 16, 2021Assignee: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Chee Kay Chow, Thian Hwee Tan, Wedanni Linsangan Micla, Enrique Jr Sarile, Mario Arwin Fabian, Dennis Tresnado, Antonino Ii Milanes, Ming Koon Ang, Kian Soo Lim, Mauro Jr. Dionisio, Teddy Joaquin Carreon
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Publication number: 20200161351Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.Type: ApplicationFiled: November 18, 2019Publication date: May 21, 2020Inventors: Hua Hong TAN, Chee Kay CHOW, Thian Hwee TAN, Wedanni Linsangan MICLA, Enrique Jr SARILE, Mario Arwin FABIAN, Dennis TRESNADO, Antonino II MILANES, Ming Koon ANG, Kian Soo LIM, Mauro Jr. DIONISIO, Teddy Joaquin CARREON
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Patent number: 10566369Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.Type: GrantFiled: December 13, 2017Date of Patent: February 18, 2020Assignee: UTAC Headquarters Pte. Ltd.Inventors: Tim Thian Hwee Tan, Boon Pek Liew, Chee Kay Chow, Teddy Joaquin Carreon
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Publication number: 20180182801Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.Type: ApplicationFiled: December 13, 2017Publication date: June 28, 2018Inventors: Tim Thian Hwee TAN, Boon Pek LIEW, Chee Kay CHOW, Teddy Joaquin CARREON
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Patent number: 9312240Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.Type: GrantFiled: October 23, 2014Date of Patent: April 12, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Kriangsak Sae Le, Chee Kay Chow
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Publication number: 20150061101Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.Type: ApplicationFiled: October 23, 2014Publication date: March 5, 2015Inventors: Kriangsak Sae LE, Chee Kay CHOW