Patents by Inventor Chee Kiang Yew
Chee Kiang Yew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7089661Abstract: A method is disclosed for packaging a small size memory card, including xD Picture card, Memory Stick™, Secure Digital™ (SD) card, SmartMedia™ (SM) card, Multimedia card (MMC), CompactFlash™ (CF) card and PC card, by moulding over to encapsulate a populated printed circuit board (PCB) (10) to form the standard external dimensions and features of the memory card. The method comprises holding the populated PCB (10) in place in a cavity (44) of at least one mould piece; and moulding over both sides of the populated printed circuit board (10) to encapsulate said board. Various embodiments are disclosed, including means for holding the populated PCB (10) in the moulding cavity (44) for the encapsulation process, which includes transfer moulding and injection moulding processes, one or more moulding steps, and moulding over one part of one side of said board before the other side, and/or simultaneously moulding over both sides of said board.Type: GrantFiled: April 11, 2003Date of Patent: August 15, 2006Inventors: Piau Fong, Chee Kiang Yew, Colin Chun Sing Lum, Matthew Keng Siew Chua
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Patent number: 7042070Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.Type: GrantFiled: July 2, 2003Date of Patent: May 9, 2006Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Masazumi Amagai
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Publication number: 20040245674Abstract: The present invention provides methods for packaging small size memory cards wherein the methods comprise molding over a populated printed circuit board, thereby an encapsulated memory card is obtained with desirable external dimensions and features. In one aspect of the invention, methods are provided for preventing mold bleed underneath of the contact pads of memory cards. In one embodiment, the mold bleeding is prevented by using slidable holding pins that exert pressure directly upon the contact pins during the molding process. In another embodiments, the mold bleeding is prevented by covering the contact pads with temporary substrate coverage during the molding process. In yet another embodiment, the mold bleeding is prevented by using pressing edges that exert pressure directly upon the area of contact pads during the molding process. In still another embodiment, the mold bleeding is prevented by using vacuum pressure to secure the populated PCB onto the bottom of a molding apparatus.Type: ApplicationFiled: April 8, 2004Publication date: December 9, 2004Inventors: Chee Kiang Yew, Piau Fong, Keng Siew Matthew Chua
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Publication number: 20040201969Abstract: Method for packaging small size memory cards A method is disclosed for packaging a small size memory card, including xD Picture card, Memory Stick™, Secure Digital™ (SD) card, SmartMedia™ (SM) card, Multimedia card (MMC), CompactFlash™ (CF) card and PC card, by moulding over to encapsulate a populated printed circuit board (PCB) (10) to form the standard external dimensions and features of the memory card.Type: ApplicationFiled: April 11, 2003Publication date: October 14, 2004Inventors: Piau Fong, Chee Kiang Yew, Colin Lum Chun Sing, Matthew Chua Keng Siew
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Patent number: 6768646Abstract: An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70), a plurality of pads (100) centrally disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) adhered to the second surface (84) of the substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the openings (86) to adhere the chip (50) to the substrate (70) and surrounding the wire bonding (80), is disclosed.Type: GrantFiled: July 14, 1998Date of Patent: July 27, 2004Assignee: Texas Instruments IncorporatedInventors: Fung Leng Chen, Chee Kiang Yew, Pang Hup Ong
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Publication number: 20040004283Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.Type: ApplicationFiled: July 2, 2003Publication date: January 8, 2004Inventors: Chee Kiang Yew, Masazumi Amagai
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Patent number: 6602803Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.Type: GrantFiled: September 22, 1999Date of Patent: August 5, 2003Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Masazumi Amagai
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Patent number: 6468831Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.Type: GrantFiled: March 16, 2001Date of Patent: October 22, 2002Assignee: Texas Instruments IncorporatedInventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
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Publication number: 20020130397Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.Type: ApplicationFiled: September 22, 1999Publication date: September 19, 2002Inventors: CHEE KIANG YEW, MASAZUMI AMAGAI
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Patent number: 6387729Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: July 6, 2001Date of Patent: May 14, 2002Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Patent number: 6365833Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: February 22, 2000Date of Patent: April 2, 2002Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Publication number: 20020000648Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.Type: ApplicationFiled: March 16, 2001Publication date: January 3, 2002Inventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
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Publication number: 20020001882Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: ApplicationFiled: July 6, 2001Publication date: January 3, 2002Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Patent number: 6278616Abstract: A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.Type: GrantFiled: July 7, 1998Date of Patent: August 21, 2001Assignee: Texas Instruments IncorporatedInventors: Tito Gelsomini, Chee Kiang Yew, Yong Khim Swee
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Patent number: 6274929Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.Type: GrantFiled: September 1, 1998Date of Patent: August 14, 2001Assignee: Texas Instruments IncorporatedInventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
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Patent number: 6218202Abstract: A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.Type: GrantFiled: October 6, 1998Date of Patent: April 17, 2001Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Kim Hoch Tey, Min Yu Chan, Jeffrey Tuck Fock Toh
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Patent number: 6091140Abstract: In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip.At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate.Type: GrantFiled: October 23, 1998Date of Patent: July 18, 2000Assignee: Texas Instruments IncorporatedInventors: Tuck Fook Toh, Chew Weng Leong, Chee Kiang Yew, Pang Hup Ong
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Patent number: 6087203Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.Type: GrantFiled: December 19, 1997Date of Patent: July 11, 2000Assignee: Texas Instruments IncorporatedInventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
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Patent number: 6084306Abstract: An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18, 118), respectively, disposed on the upper and lower surfaces (92, 94) of the first layer (76), at least one of the upper conduits (18) electrically connected to at least one of the lower conduits (118), a plurality of pads (100) disposed on the second layer (78), vias (84) that electrically connect the pads (100) to the lower conduits (118) and a chip (50) adhered to the second layer (78) having bonding pads (120) at least one of which is electrically connected to at least one of the routing pads (82), is disclosed.Type: GrantFiled: May 29, 1998Date of Patent: July 4, 2000Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Kian Teng Eng, Ji Cheng Yang
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Patent number: 6049129Abstract: An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.Type: GrantFiled: December 19, 1997Date of Patent: April 11, 2000Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Yong Khim Swee, Min Yu Chan, Pang Hup Ong, Anthony Coyle