Patents by Inventor Chee Tee Chua

Chee Tee Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7573081
    Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 11, 2009
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
  • Publication number: 20070007623
    Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
    Type: Application
    Filed: September 11, 2006
    Publication date: January 11, 2007
    Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
  • Patent number: 7105420
    Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: September 12, 2006
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
  • Patent number: 6348385
    Abstract: The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: February 19, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Randall Cher Liang Cha, Tae Jong Lee, Alex See, Lap Chan, Chee Tee Chua
  • Patent number: 6284610
    Abstract: A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: September 4, 2001
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Randall Cher Liang Cha, Chee Tee Chua, Kin Leong Pey, Lap Chan
  • Patent number: 6221727
    Abstract: A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 24, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Johnny Kok Wai Chew, Cher Liang Cha, Chee Tee Chua
  • Patent number: 6140197
    Abstract: A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the dielectric layer. The intermetal dielectric layer is patterned whereby a plurality of openings are made through the intermetal dielectric layer to the semiconductor substrate. Thereafter, an oxide layer is deposited overlying the intermetal dielectric layer and capping the plurality of openings thereby forming air gaps within the intermetal dielectric layer. A metal plug is formed through the oxide layer and the intermetal dielectric layer to the metal line.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: October 31, 2000
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Shau-Fu Sanford Chu, Kok Wai Johnny Chew, Chee Tee Chua, Cher Liang Cha
  • Patent number: 6121130
    Abstract: A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm.sup.2. Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: September 19, 2000
    Assignees: Chartered Semiconductor Manufacturing Ltd., National Univ. of Singapore, Nanyang Technology Univ.
    Inventors: Chee Tee Chua, Yuan-Ping Lee, Mei Sheng Zhou, Lap Chan