Abstract: A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.

Abstract: A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Abstract: An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Abstract: Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch, and an inter-cluster communication mechanism. This invention uses a way of time sharing or time multiplexing to alternatively execute a single program thread across multiple parallel clusters. It minimizes the hardware resources for complicated forwarding circuitry or bypassing mechanism by greatly increasing the tolerance of instruction latency in the datapath. This invention may distribute function units serially into pipeline stages to support composite instructions. The performance and the code sizes of application programs can therefore be significantly improved with these composite instructions, of which the introduced latency can be completely hidden in this invention. This invention also has the advantage of being compatible with the program codes developed on conventional multi-cluster architectures.

Abstract: A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Abstract: A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Abstract: A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.

Abstract: A unified single-core and multi-mode processor and its program execution method are provided. In an embodiment of this processor, a single instruction stream is different types of instructions randomly arranged in thereof. The processor switches its modes based on the type of a fetched instruction to execute the program corresponding to the fetched instruction.

Abstract: An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Abstract: A floating point arithmetic unit for embedded digital signal processing is provided with the ability of tracking the exponent portion of numerals using static analyzing technology efficiently and of low-power consumption. A fix adding unit with a simplified mantissa alignment device and simplified normalizing device arranged at the input end and output end, a fix multiplying unit with a simplified normalizing device arranged at the output end, and a shifter are included in the floating point arithmetic unit. A shift control method in accordance the floating point arithmetic unit is also provided to prevent overflow of the peak of the numerals. According the unit and the method, the effective precision of the arithmetic result is higher. The hardware configuration, power consumption and chip area are similar with fix point arithmetic units, while the precision is close to the floating point arithmetic units with complicated configuration.

Abstract: The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Abstract: Devices for computing discrete cosine transform, inverse discrete cosine transform or reduced ones, which require fewer transistors and less chip area, and which operate at a higher speed than those of the prior art. For example, the DCT/IDCT processor in the present invention essentially includes a matrix summation device and a plurality of shift adders. The matrix summation device computes a plurality of binary vectors from bits of an input vector, respectively for each term of an output vector. The shift-adding means respectively compute the terms of the output vector by sequentially left-shifting and adding the corresponding binary vectors.

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.