Patents by Inventor Chen-Cheng Lin

Chen-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11993782
    Abstract: Provided is a lentivirus packaging system, which comprises: a transfer plasmid comprising a nucleotide sequence of TAR-reserved-chimeric 5? long terminal repeat (LTR); at least one packaging plasmid comprising a nucleotide sequence encoding TAR RNA binding protein, a nucleotide sequence of rev gene, a nucleotide sequence of gag gene, and a nucleotide sequence of pol gene; and an envelope plasmid. Due to the expression of gene of TAR RNA binding protein by the packaging plasmids, the produced lentivirus has higher virus titer and can improve the transduction rate and the gene delivery efficiency during cell transduction. The present invention further provides a method of improving lentivirus production in a host cell, which comprises using the lentivirus packaging system to transfect the host cell. The present invention further provides a cell transduced by the lentivirus and a method of using the cell for treating cancer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 28, 2024
    Assignee: PELL BIO-MED TECHNOLOGY CO., LTD.
    Inventors: Wei-Chi Lin, Ssu-Yu Chou, Yao-Cheng Yang, Chien-Ting Lin, Chen-Lung Lin
  • Publication number: 20240170543
    Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240153970
    Abstract: The invention provides a display device and a display panel. The display device includes the display panel and a reading circuit. The display panel includes an upper substrate, a lower substrate, a thin-film transistor (TFT) layer, and a photosensitive circuit. The TFT layer is disposed between the upper substrate and the lower substrate. A plurality of TFTs of a pixel array of the display panel are disposed in the TFT layer. The photosensitive circuit is disposed in the TFT layer to sense an ambient light. The reading circuit is coupled to the photosensitive circuit to read a sensing result.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 9, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Ya-Hsiang Tai, Yi-Cheng Yuan, Chen-Yu Lin
  • Patent number: 11977655
    Abstract: A computer-implemented method, a computer system, and computer program product for associating security events. The method includes obtaining a result of implementation of one or more Locality-Sensitive Hashing (LSH) functions to feature data of a first event detected by a first device. The method also includes mapping the result to one or more positions in a data structure. In response to data elements of the one or more positions indicating first information associating with the one or more positions exists in a storage, the method includes obtaining the first information from the storage. The method further includes sending the first information to the first device.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 7, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jia-Sian Jhang, Chen-Yu Kuo, Hsiao-Yung Chen, Lu Cheng Lin, Chien Wen Jung
  • Publication number: 20240136298
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11967563
    Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 11966546
    Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: April 23, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
  • Publication number: 20240114614
    Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: HO-CHIEH YU, CHEN-CHENG-LUNG LIAO, CHUN-YU LIN, JASON AN CHENG HUANG, CHIH-CHUAN LIANG, KUN-TZU CHEN, NAI-HIS HU, LIANG-YO CHEN
  • Publication number: 20240105632
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Publication number: 20240105654
    Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Chita CHUANG, Yao-Chun CHUANG, Tsung-Shu LIN, Chen-Cheng KUO, Chen-Shien CHEN
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240097216
    Abstract: The present invention discloses a detection device and a probe module thereof, wherein an electrical connection path between a battery detection frame and a battery under test is provided via the probe module. The probe module includes a base, a first polarity plate, a second polarity plate, a first upper connection group, a second upper connection group, a first lower connection member and a second lower connection member. Via the first polarity plate, the first upper connection group is correspondingly coupled to the battery detection frame, and the first lower connection member is correspondingly coupled to the battery under test. Via the second polarity plate, the second upper connection group is correspondingly coupled to the battery detection frame, and the second lower connection member is correspondingly coupled to the battery under test. Thus, it is not necessary to process a cable having been fixed on the battery detection frame when the probe module is replaced.
    Type: Application
    Filed: June 8, 2023
    Publication date: March 21, 2024
    Inventors: CHUAN-TSE LIN, CHEN-CHOU WEN, SHIH-CHIN TAN, WEN-CHUAN CHANG, YING-CHENG CHEN
  • Publication number: 20240096816
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11933945
    Abstract: An optical lens includes a first lens group and a second lens group. The first lens group has at least two lenses that include at least one aspheric lens, the second lens group has at least four lenses that includes at least one aspheric lens, and a total number of lenses with refractive powers in the optical lens is smaller than nine. The first and the second lens groups include a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens in order from the magnified side to the minified side. The first lens to the sixth lens have respective refractive powers of negative, negative, positive, positive, negative and positive.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 19, 2024
    Assignee: RAYS OPTICS INC.
    Inventors: Ching-Lung Lai, Ying-Hsiu Lin, Chen-Cheng Lee
  • Publication number: 20240087954
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: JING-CHENG LIN, YING-CHING SHIH, PU WANG, CHEN-HUA YU
  • Publication number: 20240079381
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Chen-Hua YU, An-Jhih SU, Jing-Cheng LIN, Po-Hao TSAI
  • Publication number: 20230350509
    Abstract: A touch display device includes a driving substrate, a display medium layer, a common electrode layer, a touch electrode layer, and a protective layer. The display medium layer is disposed on the driving substrate. The common electrode layer is in direct contact with and disposed on the display medium layer. The common electrode layer includes multiple common electrodes, and two adjacent of the common electrodes have a spacing between each other. The touch electrode layer is disposed on the display medium layer. The touch electrode layer and the common electrode layer define a touch structure layer. The protective layer is disposed on the touch electrode layer.
    Type: Application
    Filed: March 13, 2023
    Publication date: November 2, 2023
    Applicant: E Ink Holdings Inc.
    Inventors: Chen Cheng Lin, Mondal Somnath, Fang Chia Hu, Hung Wei Tseng
  • Publication number: 20230259234
    Abstract: A touch display device includes a reflective display module, a touch sensing layer, a light guide member, a ground shielding layer, and a first adhesive layer. The touch sensing layer is disposed on a display surface of the reflective display module, and the light guide member is disposed between the reflective display module and the touch sensing layer. The ground shielding layer is in contact with the light guide member and located between the reflective display module and the touch sensing layer. The ground shielding layer electrically connects to one of the reflective display module and the touch sensing layer to electrically connect to a ground potential through the one of the reflective display module and the touch sensing layer. The first adhesive layer is disposed between the light guide member and the reflective display module, and is located between the ground shielding layer and the reflective display module.
    Type: Application
    Filed: December 30, 2022
    Publication date: August 17, 2023
    Applicant: E Ink Holdings Inc.
    Inventors: Chen Cheng Lin, Hung Wei Tseng, Fang Chia Hu
  • Patent number: 11592940
    Abstract: A touch display apparatus includes a first sensing element, a flexible display device, and a second sensing element. The flexible display device is disposed below the first sensing element. The flexible display device is located between the first sensing element and the second sensing element. The second sensing element includes a pressure sensing layer and a reaction force layer. The pressure sensing layer is located between the flexible display device and the reaction force layer.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 28, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Hung-Wei Tseng, Chen-Cheng Lin, Yi-Chun Kuo