Abstract: Provided is a lentivirus packaging system, which comprises: a transfer plasmid comprising a nucleotide sequence of TAR-reserved-chimeric 5? long terminal repeat (LTR); at least one packaging plasmid comprising a nucleotide sequence encoding TAR RNA binding protein, a nucleotide sequence of rev gene, a nucleotide sequence of gag gene, and a nucleotide sequence of pol gene; and an envelope plasmid. Due to the expression of gene of TAR RNA binding protein by the packaging plasmids, the produced lentivirus has higher virus titer and can improve the transduction rate and the gene delivery efficiency during cell transduction. The present invention further provides a method of improving lentivirus production in a host cell, which comprises using the lentivirus packaging system to transfect the host cell. The present invention further provides a cell transduced by the lentivirus and a method of using the cell for treating cancer.

Abstract: A slip defect management apparatus and method efficiently avoids processing of bad data read from a DVD and provides very rapid slipping of defective sectors in a write operation.

Abstract: Speed of operation is increased in a DVD error correcting apparatus by first correcting rows of DVD data from PI check bytes in a PI engine and storing it in SRAM and feeding the corrected PI data into SDRAM and a PO engine, where only the syndromes are stored in an 8K SRAM, and only the bytes to be corrected are written to SDRAM. Speed of operation is enhanced by transferring most of the random and small burst of data to SRAM in big bursts with a minimum number of random accesses to the main SDRAM or DRAM.

Abstract: A slip defect management apparatus and method efficiently avoids processing of bad data read from a DVD and provides very rapid slipping of defective sectors in a write operation.

Abstract: A method of processing a DVD bitstream includes the steps of reading the DVD bitstream, the bitstream including a sync frame. A sync window is created, the sync window being open at least during the expected timing of a sync detection signal within the sync frame. The sync pattern is detected within the sync frame and the sync detection signal is generated only when the sync pattern has been detected and the sync window is open. A DVD sync pattern detection circuit includes a sync window generator to generate a sync window signal, a sync pattern detector, the sync pattern detector generating a sync detection signal only when both a sync pattern is detected in a DVD input stream and the sync window signal is asserted. A read channel bit counter generates a read counter signal to control the sync window generator, the read channel bit counter being reset when the sync pattern detector detects the sync pattern.

Abstract: A method of and apparatus for providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) bus. The digital interface system includes a number of functional elements in addition to a PCI interface element. Each of the functional elements and the PCI interface element receives a system clock signal via a clock tree. The clock tree derives individual clock signals from the system clock and provides these individual clock signals to each of the functional elements. The clock tree is balanced such that each clock transition occurs at each of the functional elements, other than the PCI interface element, at substantially the same time. Clock balancing is achieved through appropriate circuit layout and insertion of delay elements. The clock tree also derives a clock signal for the PCI interface element from the system clock signal.

Abstract: An apparatus for and method of separating protocol header information from content data in an IEEE 1394-1995 serial bus network. A receiving node receives isochronous data packets from a transmitting node via a serial bus. Each packet can include a data portion in addition to protocol header information, although not every packet necessarily includes the data portion. Each incoming packet is loaded into a buffer in the receiver as the packet is being received. The protocol header information is removed and stored in sequence in a first block of memory. This is accomplished by placing an input_more direct memory access (DMA) instruction into a next instruction register and, then, executing the instruction. In addition, the receiver is conditioned for removing the data portion from the buffer by loading an input_last DMA instruction into the next instruction register.

Abstract: A system and method for efficiently designing integrated circuits provides a verification manager for verifying an integrated circuit design, a synthesis manager for synthesizing the integrated circuit design, a backend manager for implementing the integrated circuit design, and a processor for simultaneously controlling the verification manager, the synthesis manager, and the backend manager to create the integrated circuit design. The system and method generates a series of regression checkpoints controlled by the verification manager, and a series of timing checkpoints controlled by the synthesis manager to facilitate and expedite the integrated circuit design procedure.