Abstract: This is a type of pluggable optoelectronic transceiver that operates while immersed in cooling fluid for data transmission. The pluggable optoelectronic transceiver consists of an optical module, fluid separating colloid, and colloid separating cover. The fluid separating colloid serves to keep the cooling fluid separate from the optical module, while the colloid separating cover further ensures separation between the fluid separating colloid and the optical module. This design prevents the cooling fluid and the fluid separating colloid from infiltrating the optical module and affecting its operation.

Abstract: The immersion cooling apparatus includes a cooling tank having a cooling liquid; a cable having a first end and a second end and a protection tube wrapping the cable. The first end connects a first connector, and the second end connects a second connector. At least one of the first end and the second end is located in the cooling tank. The protection tube is configured to separate the cable and the cooling liquid, and the protection tube includes at least one of a hard tube, a soft tube, or a thermal shrinking tube.

Abstract: A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.

Abstract: A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first and second epitaxial layers, and first and second semiconductor layers. The second epitaxial layer is disposed on the first epitaxial layer. The first semiconductor layer extends from above the second epitaxial layer to a top surface of the second epitaxial layer. A vertically extending region of the first semiconductor layer has a body portion and an extending portion extending from a bottom end of the body portion to the second epitaxial layer. A width of the body portion is greater than a width of the extending portion. The second semiconductor layer is disposed on the second epitaxial layer, and laterally surrounds the vertically extending region of the first semiconductor layer. A portion of the second semiconductor layer extends between and overlaps with the body portion of the first semiconductor layer and the second epitaxial layer.

Abstract: A non-volatile memory structure including a substrate, a select gate, a control gate, and a charge storage layer is provided. There is a trench in the substrate. The select gate is disposed in the trench. The control gate is disposed in the trench and is located on the select gate. The charge storage layer is disposed between the control gate and the select gate and between the control gate and the substrate. The charge storage layer includes a nitride layer, a first oxide layer, and a second oxide layer. The nitride layer is disposed on the select gate and on two sidewalls of the trench. The nitride layer is a continuous structure. The first oxide layer is disposed between the nitride layer and the select gate. The second oxide layer is disposed between the control gate and the nitride layer.

Abstract: Provided are a transistor and a manufacturing method thereof. The transistor includes a substrate, a collector, a base, an emitter and a diffusion barrier layer. The collector is disposed on the substrate. The base is disposed on the collector. The emitter is disposed on the base. The diffusion barrier layer is disposed between the base and the emitter. An upper portion of the base includes a doped layer, and the diffusion barrier layer is disposed on the doped layer. The emitter, the doped layer, and the collector are of a first conductive type, and the rest of the base is of a second conductive type.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first and second epitaxial layers, and first and second semiconductor layers. The second epitaxial layer is disposed on the first epitaxial layer. The first semiconductor layer extends from above the second epitaxial layer to a top surface of the second epitaxial layer. A vertically extending region of the first semiconductor layer has a body portion and an extending portion extending from a bottom end of the body portion to the second epitaxial layer. A width of the body portion is greater than a width of the extending portion. The second semiconductor layer is disposed on the second epitaxial layer, and laterally surrounds the vertically extending region of the first semiconductor layer. A portion of the second semiconductor layer extends between and overlaps with the body portion of the first semiconductor layer and the second epitaxial layer.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.

Abstract: A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

Abstract: A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.

Abstract: A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a substrate. The exposed sacrificial layer is removed by using the patterned mask layer as an etching mask and the protective layer as an etching stop layer. Spacers are formed on the sidewalls of the sacrificial layer. Subsequently, the exposed protective layer and the conductive layer are removed by using the spacers and the sacrificial layer as etching masks, so as to form gate structures. By forming the protective layer on the conductive layer, the present invention can avoid the top surface of each gate structure from generating sharp corners and also increase the width of each gate structure.