Patents by Inventor Chen Fan
Chen Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240162319Abstract: Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion.Type: ApplicationFiled: November 14, 2022Publication date: May 16, 2024Inventors: Su Chen Fan, Albert M. Young, Ruilong Xie, Prabudhya Roy Chowdhury, Jay William Strane
-
Patent number: 11985010Abstract: Aspects of this disclosure relate to a time-division duplex (TDD) multiple-input multiple-output (MIMO) system that includes a plurality of nodes. The plurality of nodes collectively includes antennas divided into groups. Reference signals can be transmitted from each group of antennas to one or more other groups of antennas during respective time slots. Channel estimates can be generated based on the received reference signals. The channel estimates can be jointly processed to generate calibration coefficients. Each calibration coefficient can represent a ratio associated with a transmit coefficient and a receive coefficient. Example algorithms for the joint processing are disclosed.Type: GrantFiled: July 7, 2022Date of Patent: May 14, 2024Assignee: Virewirx, Inc.Inventors: Jinghu Chen, Wanlun Zhao, Tamer Adel Kadous, Peter John Black, Michael Mingxi Fan
-
Publication number: 20240155647Abstract: The present disclosure relates to an electronic device, a wireless communication method, and a computer-readable storage medium. The electronic device in the present disclosure comprises: a processing circuit, which is configured to: generate first downlink control information (DCI), wherein the first DCI comprises scheduling information of a plurality of data channels; and carries multiple pieces of first DCI by using the data channels. By means of using the electronic device, the wireless communication method and the computer-readable storage medium of the present disclosure, when DCI schedules a plurality of data channels, the probability of a UE correctly decoding the DCI can be improved, that is, the reliability of DCI transmission can be improved.Type: ApplicationFiled: March 25, 2022Publication date: May 9, 2024Applicant: Sony Group CorporationInventors: Tingting FAN, Chen SUN
-
Patent number: 11978570Abstract: An antioxidant conductive thermal paste and a method of manufacturing the same are provided. The antioxidant conductive thermal paste includes a reactive monomer, a thermosetting resin, a polymerization inhibitor, an electrically conductive filler, and a thixotropic agent. The method consists of the steps of mixing a reactive monomer, a thermosetting resin, and a polymerization inhibitor evenly to get a first polymer mixture, and adding an electrically conductive filler and a thixotropic agent into the first polymer mixture in turn and blending the mixture evenly to obtain an antioxidant conductive thermal paste with good adherence, high electrical conductivity, high thermal conductivity, improved thermal-mechanical fatigue resistance or mechanical fatigue resistance.Type: GrantFiled: August 21, 2023Date of Patent: May 7, 2024Assignee: Geckos Technology Corp.Inventors: Wei-Chen Chang, Chen-Yen Fan, Ping-Hung Chen, Tsung-Huan Sheng
-
Publication number: 20240142669Abstract: An electronic device including a protective substrate is provided. The protective substrate includes a substrate and an anti-reflection layer. The anti-reflection layer is disposed on the substrate. The anti-reflection layer includes a first sublayer to an nth sublayer sequentially arranged on the substrate, where n is greater than 1, and a product range of a thickness and a refractive index of the nth sublayer ranges from 100 nm to 170 nm.Type: ApplicationFiled: September 21, 2023Publication date: May 2, 2024Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.Inventors: Kuan-Chen Chen, Liang-Cheng Ma, Ming-Er Fan
-
STACKED FIELD EFFECT TRANSISTOR STRUCTURE WITH INDEPENDENT GATE CONTROL BETWEEN TOP AND BOTTOM GATES
Publication number: 20240145473Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Tsung-Sheng Kang, Su Chen Fan, Jingyun Zhang, Ruqiang Bao, Son Nguyen -
Patent number: 11965833Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.Type: GrantFiled: November 26, 2020Date of Patent: April 23, 2024Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
-
Publication number: 20240128345Abstract: A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.Type: ApplicationFiled: October 12, 2022Publication date: April 18, 2024Inventors: Ruilong Xie, Su Chen Fan, Ravikumar Ramachandran, Julien Frougier
-
Patent number: 11961629Abstract: An antioxidant conductive thermal paste and a method of manufacturing the same are provided. The antioxidant conductive thermal paste includes a reactive monomer, a thermosetting resin, a polymerization inhibitor, an electrically conductive filler, and a thixotropic agent. The method consists of the steps of mixing a reactive monomer, a thermosetting resin, and a polymerization inhibitor evenly to get a first polymer mixture, and adding an electrically conductive filler and a thixotropic agent into the first polymer mixture in turn and blending the mixture evenly to obtain an antioxidant conductive thermal paste with good adherence, high electrical conductivity, high thermal conductivity, improved thermal-mechanical fatigue resistance or mechanical fatigue resistance.Type: GrantFiled: December 8, 2022Date of Patent: April 16, 2024Assignee: Geckos Technology Corp.Inventors: Wei-Chen Chang, Chen-Yen Fan, Ping-Hung Chen, Tsung-Huan Sheng
-
Publication number: 20240113176Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.Type: ApplicationFiled: October 4, 2022Publication date: April 4, 2024Inventors: Ruilong Xie, Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Su Chen Fan, Shogo Mochizuki, SON NGUYEN
-
Publication number: 20240112985Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.Type: ApplicationFiled: October 4, 2022Publication date: April 4, 2024Inventors: Ruilong Xie, Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Su Chen Fan, Shogo Mochizuki, SON NGUYEN
-
Patent number: 11947261Abstract: A method of making photolithography mask plate is provided. The method includes: providing a carbon nanotube layer on a substrate; depositing a chrome layer on the carbon nanotube layer, wherein the chrome layer includes a first patterned chrome layer and a second patterned chrome layer, the first patterned chrome layer is located on the carbon nanotube layer, and the second patterned chrome layer is deposited on the substrate corresponding to holes of the carbon nanotube layer; transferring the carbon nanotube layer with the first patterned chrome layer thereon from the substrate to a base, and the carbon nanotube layer being in contact with the base; and depositing a cover layer on the first patterned chrome layer.Type: GrantFiled: January 15, 2021Date of Patent: April 2, 2024Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Mo Chen, Qun-Qing Li, Li-Hui Zhang, Yuan-Hao Jin, Dong An, Shou-Shan Fan
-
Patent number: 11947255Abstract: A method of making photolithography mask plate is provided. The method includes: providing a carbon nanotube composite structure, wherein the carbon nanotube composite structure comprises a carbon nanotube layer and a chrome layer coated on the carbon nanotube layer; locating the carbon nanotube composite structure on a substrate to expose partial surfaces of the substrate; and depositing a cover layer on the carbon nanotube composite structure.Type: GrantFiled: January 15, 2021Date of Patent: April 2, 2024Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Mo Chen, Qun-Qing Li, Li-Hui Zhang, Yuan-Hao Jin, Dong An, Shou-Shan Fan
-
Publication number: 20240099196Abstract: The disclosure provides a mower. The mower includes a vehicle frame, a walking assembly, a working assembly, a seat and a battery pack. The walking assembly includes a first walking wheel assembly and a second walking wheel assembly connected with the vehicle frame. The first walking wheel assembly and/or the second walking wheel assembly includes a main walking wheel and a hub motor, the main walking wheel is connected with the hub motor, and the hub motor is arranged outside a side of the vehicle frame. The working assembly is connected with the vehicle frame. The seat is arranged on the vehicle frame. The battery pack is lowered and mounted on the vehicle frame and extends below the seat.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Applicant: Greenworks (Jiangsu) Co., Ltd.Inventors: Qunli WEI, Dongdong SHI, Chen ZHU, Min DING, Chaoqun WANG, Fei ZHU, Jun FAN, Liang PENG
-
Patent number: 11937515Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.Type: GrantFiled: August 9, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
-
Patent number: 11935929Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.Type: GrantFiled: October 21, 2021Date of Patent: March 19, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Julien Frougier, Su Chen Fan, Ravikumar Ramachandran, Nicolas Loubet
-
Publication number: 20240087986Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
-
Publication number: 20240079461Abstract: A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Brent A. Anderson, Su Chen Fan, Jay William Strane, Ruilong Xie
-
Patent number: 11923272Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.Type: GrantFiled: April 15, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
-
Publication number: 20240071811Abstract: A stacked field effect transistor (FET) device. The device includes an opening in a shallow trench isolation (STI) region on a substrate. The device also includes an epitaxy region located on the substrate at a bottom portion of STI region in the opening. The device further includes a substrate contact that directly contacts the epitaxy region.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Su Chen Fan, Jay William Strane, Gen Tsutsui, Stuart Sieg