Patents by Inventor Chen-Fong Tsai
Chen-Fong Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990404Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.Type: GrantFiled: July 21, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240153786Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.Type: ApplicationFiled: January 11, 2024Publication date: May 9, 2024Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Publication number: 20240120314Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Patent number: 11908708Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.Type: GrantFiled: September 20, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Publication number: 20240055480Abstract: A method includes forming fin structures upwardly extending above a semiconductor substrate; conformally depositing a first dielectric layer over the fin structures; depositing a flowable oxide over the first dielectric layer and between the fin structures; performing, at a temperature lower than about 500° C., a steam annealing process on the flowable oxide to cure the flowable oxide; after performing the steam annealing process, etching the cured flowable oxide until a top surface of the cured flowable oxide is lower than top surfaces of the fin structures; forming a second dielectric layer over the cured flowable oxide; forming a first gate structure extending across a first one of the fin structures and a second gate structure extending across a second one of the fin structures; forming first sources/drain regions on the first one of the fin structures and second sources/drain regions on the second one of the fin structures.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Chen TENG, Chen-Fong TSAI, Li-Chi YU, Huicheng CHANG, Yee-Chia YEO
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Patent number: 11901189Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.Type: GrantFiled: November 18, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Fong Tsai, Ya-Lun Chen, Tsai-Yu Huang, Yahru Cheng, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11855040Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.Type: GrantFiled: October 8, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Publication number: 20230386852Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Chen-Fong TSAI, Ya-Lun CHEN, Tsai-Yu HUANG, Yahru CHENG, Huicheng CHANG, Yee-Chia YEO
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Publication number: 20230067088Abstract: The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Han-De CHEN, Yun-Chen TENG, Chen-Fong TSAI, Jyh-Cherng SHEU, Huicheng CHANG, Yee-Chia YEO
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Publication number: 20230063975Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Yun Chen Teng, Chen-Fong Tsai, Han-De Chen, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230067346Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Han-De Chen, Yun Chen Teng, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230042726Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.Type: ApplicationFiled: May 6, 2022Publication date: February 9, 2023Inventors: Yun Chen Teng, Chen-Fong Tsai, Li-Chi Yu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230019415Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.Type: ApplicationFiled: January 18, 2022Publication date: January 19, 2023Inventors: Han-De Chen, Cheng-I Chu, Yun Chen Teng, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230010038Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.Type: ApplicationFiled: September 10, 2021Publication date: January 12, 2023Inventors: Cheng-I Chu, Han-De Chen, Chen-Fong Tsai, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220406621Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.Type: ApplicationFiled: September 20, 2021Publication date: December 22, 2022Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Publication number: 20220367410Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.Type: ApplicationFiled: October 8, 2021Publication date: November 17, 2022Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
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Publication number: 20220367249Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.Type: ApplicationFiled: July 16, 2021Publication date: November 17, 2022Inventors: Chieh Chang, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220359369Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.Type: ApplicationFiled: July 21, 2021Publication date: November 10, 2022Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220344197Abstract: A method includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. The second wafer is brought into physical contact with the first wafer. A relative distance between the first wafer and the second wafer is monitored using a distance sensor. A pressure of a vacuum zone on the second wafer chuck is controlled using feedback from the distance sensor. The bonded first wafer and second wafer are removed from the first wafer chuck.Type: ApplicationFiled: November 22, 2021Publication date: October 27, 2022Inventors: Chieh Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220262925Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: ApplicationFiled: May 17, 2021Publication date: August 18, 2022Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo