Patents by Inventor Chen Gaist
Chen Gaist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11637557Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.Type: GrantFiled: February 14, 2022Date of Patent: April 25, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Publication number: 20220173741Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Patent number: 11283454Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: GrantFiled: July 6, 2020Date of Patent: March 22, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Publication number: 20220021393Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: ApplicationFiled: July 6, 2020Publication date: January 20, 2022Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Patent number: 11171816Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.Type: GrantFiled: July 30, 2020Date of Patent: November 9, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Matan Groen, Chen Gaist, Hananel Faig
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Publication number: 20210044461Abstract: A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N?<N of lookahead modules. The processing blocks are arranged in groups of L processing blocks, and each processing block in a group receives (i) N? symbols selected for the group from among the N symbols, and (ii) a predefined speculative value of a DFE output, and produces, based on the N? symbols and on the predefined speculative value, N? respective lookahead values. N??1 of the N? lookahead values are used in a chained calculation that meets a timing constraint that is not met by the chained calculation performed on N lookahead values. The selection logic selects one of the L lookahead values in each group of the L processing blocks for each of the N? symbols, and outputs N lookahead values in parallel.Type: ApplicationFiled: July 30, 2020Publication date: February 11, 2021Inventors: Matan Groen, Chen Gaist, Hananel Faig
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Patent number: 10879910Abstract: Methods and apparatuses are provided for locking a transmitter oscillator to a reference clock signal in a frequency domain. The apparatus includes a digital phase-frequency detector. The digital phase-frequency detector includes a mod-M counter, a mod-N counter, and a count evaluation digital circuit. The mod-M counter is designed to count reference clock cycles of a reference clock signal. The mod-N counter is designed to count local clock cycles of a local clock signal. The count evaluation digital circuit is designed to compare the counted reference clock cycles and the local clock cycles with a predefined register setting to generate a control signal as a feedback signal. The control signal is transmitted to the transmitter oscillator through a frequency-locked loop circuit for adjusting the frequency of the transmitter oscillator to be consistent with the reference clock signal.Type: GrantFiled: September 4, 2019Date of Patent: December 29, 2020Assignee: Mellanox Technologies Ltd.Inventors: Thorkild Franck, Ulrik Wismar, Ran Sela, Chen Gaist, Afek Bernhard
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Patent number: 10778406Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: GrantFiled: November 26, 2018Date of Patent: September 15, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Chen Gaist, Ran Ravid, Aviv Berg, Lavi Koch
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Publication number: 20200169379Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: ApplicationFiled: November 26, 2018Publication date: May 28, 2020Inventors: Chen Gaist, Ran Ravid, Aviv Berg, Lavi Koch
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Patent number: 9876727Abstract: A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.Type: GrantFiled: March 23, 2015Date of Patent: January 23, 2018Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Chen Gaist, Ran Ravid, Liron Mulla, Avner Hadash
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Publication number: 20160285776Abstract: A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Inventors: Chen Gaist, Ran Ravid, Liron Mulla, Avner Hadash
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Patent number: 9344117Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.Type: GrantFiled: March 15, 2013Date of Patent: May 17, 2016Assignee: Mellanox Technologies, Ltd.Inventors: Liron Mula, Ran Ravid, Chen Gaist, Omer Sella, Oren Tzvi Sela
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Publication number: 20140281840Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Mellanox Technologies Ltd.Inventors: Liron Mula, Ran Ravid, Chen Gaist, Omer Sela, Oren Tzvi Sela