Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.

Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.

Abstract: The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

Abstract: A wafer is polished by performing a chemical reaction to change a property of a first portion of a material layer on the wafer using a first chemical substance. A first rinse is performed to remove the first chemical substance and retard the chemical reaction. A mechanical polishing process is then performed to remove the first portion of the material layer.

Abstract: The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.

Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

Abstract: A method of manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer; removing a portion of the dielectric layer to form an opening exposing a portion of the conductive layer; filling a ruthenium-containing material in the opening and in contact with the dielectric layer; and polishing the ruthenium-containing material using a slurry including an abrasive and an oxidizer selected from the group consisting of hydrogen peroxide (H2O2), potassium periodate (KIO4), potassium iodate (KIO3), potassium permanganate (KMnO4), iron(III) nitrate (FeNO3) and a combination thereof.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including one or more oxygen molecules, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A method of forming a CMP pad includes providing a solution of a block copolymer (BCP), where the BCP includes a first segment and a second segment connected to the first segment, the second segment being different from the first segment in composition. The method further includes processing the BCP to form a polymer network having a first phase and a second phase embedded in the first phase, where the first phase includes the first segment and the second phase includes the second segment, and subsequently removing the second phase from the polymer network, thereby forming a polymer film that includes a network of pores embedded in the first phase. Thereafter, the method proceeds to combining the CMP top pad and a CMP sub-pad to form a CMP pad, where the CMP top pad is configured to engage with a workpiece during a CMP process.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.

Abstract: A method is provided and includes: measuring a surface profile of a polishing pad; obtaining a reference profile of the polishing pad; comparing the surface profile of the polishing pad with the reference profile to generate a difference result; determining a conditioning parameter value according to the difference result; and conditioning the polishing pad using the conditioning parameter value.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate including a silicon oxide layer and a metal oxide layer covering the silicon oxide layer. A CMP slurry is prepared. The CMP slurry includes plural abrasive particles bearing negative charges, a Lewis base including a (XaYb)? group, and a buffer solution. The X represents a IIIA group element or an early transitional metal, and Y represents a pnictogen element, a chalcogen element or a halogen element. The CMP slurry has a pH in a range substantially from 2 to 7. Next, a planarization operation is performed on a surface of the metal oxide layer until a surface of the silicon oxide layer exposed. The planarization operation has a high polishing selectivity of the metal oxide layer with respect to the silicon oxide layer.

Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.

Abstract: The present invention provides a foldable display support, wherein when a support arm is in a standing state, a limiting sheet is located in a limiting part of a screen support rack for blocking, so only the forward/backward tilted angle of a screen can be adjusted, thereby preventing being unstable and falling due to the gravity center being overly backward. When the support arm is folded to a horizontal state, the gravity center is lowered, and a protrusion of a first cam abuts a protrusion of a second cam, such that the second cam axially moves and pushes the limiting sheet to be released from the limiting part of the screen support rack, at this moment, the screen is enabled to be backwardly rotated and folded to a horizontal state for reducing the occupied space, thereby ensuring the folding process to be smooth and stable and preventing from falling.