Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a

Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Abstract: A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.

Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Abstract: A benzoxazine resin and a method for manufacturing the same, and a resin composition are provided. The benzoxazine resin is obtained from a condensation polymerization reaction of a phenolic compound, formaldehyde, and a primary amine compound that are used as a reactant. The phenolic compound includes a dicyclopentadiene phenol resin and bisphenol A. The primary amine compound includes 2,6-dimethylaniline and m-xylylenediamine. The resin composition includes the benzoxazine resin, an epoxy resin, and a bismaleimide resin. Based on a total weight of the benzoxazine resin, the epoxy resin, and the bismaleimide resin being 100 phr, an amount of the benzoxazine resin ranges from 30 phr to 50 phr.

Abstract: A polyphenylene ether bismaleimide resin, a method for manufacturing the same, and a resin composition are provided. The polyphenylene ether bismaleimide (PPE-BMI) resin is obtained by a condensation reaction with a maleic anhydride and a primary amine compound as reactants. The primary amine compound is a polyphenylene ether diamine.

Abstract: A polyphenylene ether bismaleimide resin, a method for manufacturing the same, and a resin composition are provided. The polyphenylene ether bismaleimide (PPE-BMI) resin is obtained by a condensation reaction with a maleic anhydride and a primary amine compound as reactants. The primary amine compound is a polyphenylene ether diamine.

Abstract: A benzoxazine resin and a method for manufacturing the same, and a resin composition are provided. The benzoxazine resin is obtained from a condensation polymerization reaction of a phenolic compound, formaldehyde, and a primary amine compound that are used as a reactant. The phenolic compound includes a dicyclopentadiene phenol resin and bisphenol A. The primary amine compound includes 2,6-dimethylaniline and m-xylylenediamine. The resin composition includes the benzoxazine resin, an epoxy resin, and a bismaleimide resin. Based on a total weight of the benzoxazine resin, the epoxy resin, and the bismaleimide resin being 100 phr, an amount of the benzoxazine resin ranges from 30 phr to 50 phr.

Abstract: A Formula of a phosphorous fire-retardant hardener having fire-retardant and heat-resistant properties as well as a low-dielectric constant. With a preparation of glass-fiber laminated board, the hardener meets UL-94V fire-retardant requirements and has a dielectric constant 5 of 4.0 (1 GHz).

Abstract: This invention provides a new dicyclopentadiene phenol and 2,6-dimethyl phenol copolymer epoxy resin with excellent heat resistance, low dielectric constant Dk, low dissipation factor Df having the formula 1. Preparation of dicyclopentadiene phenol and 2,6-dimethyl phenol copolymer epoxy resin in two steps: Step 1, reacting (a1) dicyclopentadiene phenol resin represented by formula 2 with (a2) 2,6-dimethyl phenol in the presence of acid catalyst by (a3) aldehyde compounds to synthesize dicyclopentadiene phenol-2,6-dimethyl phenol copolymer, and Step 2, reacting dicyclopentadiene phenol and 2,6-dimethyl phenol copolymer with excess epichlorhydrin under NaOH condition to prepare dicyclopentadiene phenol and 2,6-dimethyl phenol copolymer epoxy resin.