Patents by Inventor Chen-Huan Chiang
Chen-Huan Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8014753Abstract: A distributed test architecture of transmitting boundary scan Test Access Port (TAP_signals over a serial channel is disclosed. The architecture facilitates the system testing and remote field update of distributed base stations in a wireless network. The distributed test architecture enables system testing as if the distributed units are on a backplane within the same chassis by creating a plurality of logical connections between the distributed unit and the test bus using a single bit fiber line and a five bit TAP test bus.Type: GrantFiled: July 19, 2004Date of Patent: September 6, 2011Assignee: Alcatel LucentInventors: Ken L. Cheung, Chen-Huan Chiang, Kenneth Y. Ho, John A. Andersen, Bradford G. Van Treuren, Robert W. Barr, Victor J. Velasco, Dante De Rogatis
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Patent number: 7962885Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.Type: GrantFiled: December 4, 2007Date of Patent: June 14, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7958479Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.Type: GrantFiled: December 4, 2007Date of Patent: June 7, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7958417Abstract: The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level.Type: GrantFiled: January 30, 2008Date of Patent: June 7, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford G. Van Treuren
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Patent number: 7954022Abstract: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.Type: GrantFiled: January 30, 2008Date of Patent: May 31, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford G. Van Treuren
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Patent number: 7949915Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.Type: GrantFiled: December 4, 2007Date of Patent: May 24, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7602729Abstract: A slow fast programming method for efficient remote field update in distributed base stations overcomes significant fiber propagation delay associated with a remote unit by applying programming data at two clock frequencies. A fast clock frequency is used for programming data phases that do not require a response from the remote unit, and a slow clock frequency is used for programming data phases that require a response from the remote unit. Testing a base unit and a remote unit is also accomplished with more than one clock based on the test dependence on a remote response.Type: GrantFiled: July 19, 2004Date of Patent: October 13, 2009Assignee: Alcatel-Lucent USA Inc.Inventors: Paul James Wheatley, Chen-Huan Chiang
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Publication number: 20090193304Abstract: The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Tapan Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford G. Van Treuren
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Publication number: 20090193306Abstract: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Tapan Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford G. Van Treuren
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Publication number: 20090144594Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Publication number: 20090144593Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Treuren
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Publication number: 20090144592Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7284159Abstract: A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.Type: GrantFiled: August 26, 2003Date of Patent: October 16, 2007Assignee: Lucent Technologies Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang
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Publication number: 20060013146Abstract: A distributed test architecture of transmitting boundary scan Test Access Port (TAP_signals over a serial channel is disclosed. The architecture facilitates the system testing and remote field update of distributed base stations in a wireless network. The distributed test architecture enables system testing as if the distributed units are on a backplane within the same chassis by creating a plurality of logical connections between the distributed unit and the test bus using a single bit fiber line and a five bit TAP test bus.Type: ApplicationFiled: July 19, 2004Publication date: January 19, 2006Inventors: Ken Cheung, Chen-Huan Chiang, Kenneth Ho, John Andersen, Bradford Van Treuren, Robert Barr, Victor Velasco, Dante Rogatis
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Publication number: 20060013167Abstract: A slow fast programming method for efficient remote field update in distributed base stations overcomes significant fiber propagation delay associated with a remote unit by applying programming data at two clock frequencies. A fast clock frequency is used for programming data phases that do not require a response from the remote unit, and a slow clock frequency is used for programming data phases that require a response from the remote unit.Type: ApplicationFiled: July 19, 2004Publication date: January 19, 2006Inventors: Paul Wheatley, Chen-Huan Chiang
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Publication number: 20050050393Abstract: A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.Type: ApplicationFiled: August 26, 2003Publication date: March 3, 2005Inventors: Tapan Chakraborty, Chen-Huan Chiang