Abstract: Examples of the disclosure relate to communication methods and apparatuses, an access point, stations and a computer readable medium. An embodiment of the method comprises: determining, at an access point and based on determining that a direct link between stations based sensing procedure is triggered, a first station and a second station associated with the sensing procedure; and transmitting, to at least one of the first station and the second station, a sensing performing request for performing the sensing procedure. In this way, target sensing between non-access-point stations is achieved, such that sensing coverage is extended and a sensing effect is improved.

Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.

Abstract: The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.

Abstract: A system and method for generating a stained image including the steps of obtaining a first image of a key sample section; and processing the first image with a multi-modal stain learning engine arranged to generate at least one stained image, wherein the at least one stained image represents the key sample section stained with at least one stain.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: An electronic device and a method for determining scenario data of a self-driving car are provided. The method includes: obtaining training scenario data by using scenario data, a loss function and a self-driving program module; training an encoding module and a decoding module by using the training scenario data, and generating a scenario space by using the trained encoding module; obtaining a monitoring module by using the scenario space; and executing the monitoring module to determine whether current scenario data belongs to an operational design domain by using the current scenario data and the trained encoding module.

Abstract: The present invention provides a method for producing CAR T-cells enriched with stem cell-like memory T-cells (Tscm), comprised of: (1) providing PBMCs; (2) isolating of T cells from PBMCs using magnetic beads coated with T-cell specific antibodies; (3) positively selecting T cells by culturing them in the form of T cell-magnetic bead complexes; (4) adding CAR-expressing lentivirus to the activated human T cell-magnetic bead complexes, for transduction of human T cells into CAR-T cells on the human T cell-magnetic bead complexes to obtain human CAR-T cell-magnetic bead complexes; (5) obtaining human CAR-T cells by dissociating the human CAR-T cells from the human CAR-T cell-magnetic bead complexes; and (6) further culturing CAR-T cells to obtain CAR-T cells enriched with Tscm. The present invention expands T cells in a short period of time to obtain CAR-T cells enriched with Tscm, which is suitable for CAR-T immunotherapy.

Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.

Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.

Abstract: In an example, a speaker device may include a first transducer and a second transducer. The first transducer may include a first diaphragm, a first magnetic circuit, and a first voice coil disposed in a magnetic gap of the first magnetic circuit to cause vibration of the first diaphragm. The second transducer may include a second diaphragm, a second magnet circuit, and a second voice coil disposed in a magnetic gap of the second magnetic circuit to cause vibration of the second diaphragm. Further, the speaker device may include a magnetic plate having a first surface coupled to the first transducer and a second surface coupled to the second transducer. The first surface is opposite to the second surface.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: An optical proximity sensor includes a housing, an optical emitter, and an optical detector. A first light guide disposed in a first chimney of the housing is configured to direct light from the optical emitter through the first chimney towards a target location. A second light guide disposed in a second chimney of the housing is configured to direct a returned portion of the light emitted from the optical emitter through the second chimney towards the optical detector.

Abstract: Provided are a HEK293T cell strain having high dispersibility and a screening method therefor. Specifically, the present application relates to a method for screening a HEK293T cell strain suitable for serum-free suspension culture, a cell strain screened by using the method, and a method for producing a viral vector by using the cell strain.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.