Patents by Inventor Chen-Hui Hsieh
Chen-Hui Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8866260Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.Type: GrantFiled: November 12, 2009Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hau-Tai Shieh, Chen-Hui Hsieh
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Patent number: 7808753Abstract: A bias voltage monitoring circuit is disclosed which comprises a first device coupled between a positive high voltage power supply (VDD) and a first node, a second device coupled between the first node and a second node where the bias voltage is applied, and a pad coupled to the first node, wherein the first and second devices form a voltage divider and a voltage measured at the pad reflects the bias voltage, and the first device and the second device is so chosen that a voltage at the first node is always positive for a given range of the bias voltage.Type: GrantFiled: February 27, 2007Date of Patent: October 5, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ting Cheng, Chen-Hui Hsieh
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Publication number: 20100219502Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.Type: ApplicationFiled: November 12, 2009Publication date: September 2, 2010Inventors: Hau-Tai Shieh, Chen-Hui Hsieh
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Patent number: 7777361Abstract: A turbine ventilator includes a housing having a hub, a tube having a lower segment secured to the hub, a seat disposed on an upper portion of the tube, an electric generator disposed on the seat and having a rotor and an extension secured to the rotor and extended out of the generator, a carrier rotatably attached to the tube, and a number of blades each having a lower portion secured to the carrier and an upper portion secured to the extension of the rotor for rotating the extension of the rotor relative to the generator in order to generate an electric energy. The extension of the rotor includes a relatively shorter length for allowing the rotor to be effectively rotated relative to the generator by the blades.Type: GrantFiled: January 23, 2008Date of Patent: August 17, 2010Inventor: Chen-Hui Hsieh
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Patent number: 7755344Abstract: A low-voltage sub-bandgap reference circuit is disclosed. In one embodiment, the low-voltage sub-bandgap voltage reference circuit includes a differential amplifier and a first bipolar transistor with its base and collector coupled to an electrical ground. The reference circuit further includes a second bipolar transistor with base and collector coupled to the electrical ground. The reference circuit further includes a DC bias circuit supplying a predetermined voltage output between a high and low voltage terminal, the high voltage terminal being coupled to both collectors of the first and second bipolar transistors and the low voltage terminal being coupled to both bases of the first and second bipolar transistors.Type: GrantFiled: July 17, 2007Date of Patent: July 13, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chen-Hui Hsieh
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Patent number: 7663953Abstract: A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.Type: GrantFiled: March 12, 2007Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Patent number: 7663908Abstract: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.Type: GrantFiled: March 12, 2007Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Patent number: 7656726Abstract: An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory macro's data output for analysis while the memory macros are operated simultaneously.Type: GrantFiled: November 27, 2006Date of Patent: February 2, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Chia Cheng, Chen-Hui Hsieh
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Patent number: 7599212Abstract: The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.Type: GrantFiled: January 22, 2007Date of Patent: October 6, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Publication number: 20090184520Abstract: A turbine ventilator includes a housing having a hub, a tube having a lower segment secured to the hub, a seat disposed on an upper portion of the tube, an electric generator disposed on the seat and having a rotor and an extension secured to the rotor and extended out of the generator, a carrier rotatably attached to the tube, and a number of blades each having a lower portion secured to the carrier and an upper portion secured to the extension of the rotor for rotating the extension of the rotor relative to the generator in order to generate an electric energy. The extension of the rotor includes a relatively shorter length for allowing the rotor to be effectively rotated relative to the generator by the blades.Type: ApplicationFiled: January 23, 2008Publication date: July 23, 2009Inventor: Chen-Hui Hsieh
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Patent number: 7499519Abstract: A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer.Type: GrantFiled: December 12, 2007Date of Patent: March 3, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hui Hsieh, Chingwen Chang, Wei-Chia Cheng, Shih-Chieh Lin
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Patent number: 7484138Abstract: A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.Type: GrantFiled: June 9, 2006Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hui Hsieh, Kun Lung Chen, Shine Chien Chung, Grigori Grigoriev
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Publication number: 20090021234Abstract: A low-voltage sub-bandgap reference circuit is disclosed. In one embodiment, the low-voltage sub-bandgap voltage reference circuit includes a differential amplifier and a first bipolar transistor with its base and collector coupled to an electrical ground. The reference circuit further includes a second bipolar transistor with base and collector coupled to the electrical ground. The reference circuit further includes a DC bias circuit supplying a predetermined voltage output between a high and low voltage terminal, the high voltage terminal being coupled to both collectors of the first and second bipolar transistors and the low voltage terminal being coupled to both bases of the first and second bipolar transistors.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Inventor: Chen-Hui Hsieh
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Patent number: 7459350Abstract: A method for making a semiconductor device having a fuse window above a substrate is disclosed. The semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second end. A first transistor having a drain is connected to the second end of the fuse, a gate for receiving an input signal, and a source is connected to a second voltage. A second transistor having a drain is connected to the second end of the fuse, a gate, and a source is connected to the second voltage. A first diode having an anode and a cathode, the anode of the first diode is connected to the second voltage and the cathode of the first diode is connected to the second end of the fuse. A second diode having an anode and a cathode, the anode of the second diode is connected to the second end of the fuse and the cathode of the second diode is connected to the first voltage.Type: GrantFiled: August 9, 2006Date of Patent: December 2, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chen-Hui Hsieh
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Publication number: 20080225616Abstract: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Publication number: 20080225617Abstract: A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Publication number: 20080203996Abstract: A bias voltage monitoring circuit is disclosed which comprises a first device coupled between a positive high voltage power supply (VDD) and a first node, a second device coupled between the first node and a second node where the bias voltage is applied, and a pad coupled to the first node, wherein the first and second devices form a voltage divider and a voltage measured at the pad reflects the bias voltage, and the first device and the second device is so chosen that a voltage at the first node is always positive for a given range of the bias voltage.Type: ApplicationFiled: February 27, 2007Publication date: August 28, 2008Inventors: Chi-Ting Cheng, Chen-Hui Hsieh
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Publication number: 20080175037Abstract: The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.Type: ApplicationFiled: January 22, 2007Publication date: July 24, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hank Cheng, Chen-Hui Hsieh, Chung-Cheng Chou
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Publication number: 20080126901Abstract: An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory macro's data output for analysis while the memory macros are operated simultaneously.Type: ApplicationFiled: November 27, 2006Publication date: May 29, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chia Cheng, Chen-Hui Hsieh
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Publication number: 20080054990Abstract: A method for operating a plurality of charge pumps comprising: generating one or more phase-shifted clock signals; and coupling the one or more phased-shifted clock signals to the plurality of charge pumps, wherein the charge pumps are clocked at a different time to avoid excessive charging spikes caused by concurrent operation of the charge pumps.Type: ApplicationFiled: August 30, 2006Publication date: March 6, 2008Inventors: Hau-Tai Shieh, Chen-Hui Hsieh, Chung-Cheng Chou