Abstract: An imaging lens assembly has an optical axis and includes an annular structure located on an object side of the imaging lens assembly and surrounds the optical axis. The annular structure is located on an object side of the imaging lens assembly, surrounds the optical axis, and includes a first through hole, a second through hole, a first frustum surface, a second frustum surface and a third frustum surface. The first through hole is disposed on an object side of the annular structure, and the second through hole is disposed on an image side of the first through hole. The first frustum surface is disposed on the image side of the first through hole. The second frustum surface is disposed on an object side of the second through hole. The third frustum surface is disposed on an image side of the second through hole.

Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.

Abstract: The present invention provides Wnt pathway agonists and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of diseases.

Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.

Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: Nanocrystals, compositions, and methods that aid particle transport in mucus are provided. In some embodiments, the compositions and methods involve making mucus-penetrating particles (MPP) without any polymeric carriers, or with minimal use of polymeric carriers. The compositions and methods may include, in some embodiments, modifying the surface coatings of particles formed of pharmaceutical agents that have a low water solubility. Such methods and compositions can be used to achieve efficient transport of particles of pharmaceutical agents though mucus barriers in the body for a wide spectrum of applications, including drug delivery, imaging, and diagnostic applications. In certain embodiments, a pharmaceutical composition including such particles is well-suited for administration routes involving the particles passing through a mucosal barrier.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: The present application relates to control command generation methods and systems for three-dimensional surface weaving. The control command generation method comprises the steps of: rebuilding a desired three-dimensional object into a three-dimensional surface mesh; converting the three-dimensional surface mesh into readable weaving information; and generating control commands from the readable weaving information to instruct a three-dimensional surface weaving system. The control command generation method generally comprises a pipeline of software including the mesh processing, weaving map extraction and command generation. The control command generation method can enable three-dimensional surface weaving function.

Abstract: The present application relates to systems, devices and methods for three-dimensional surface weaving. The system comprises a jacquard device, a weaving device and a roller matrix. The jacquard device configured to selectively raise or lower the wrap threads to form a shed for the weft thread to travel; the weaving device configured to carry the weft thread into the shed and weave the weft thread on the wrap threads; and the roller matrix with individually controlled rotate apparatus configured to control the wrap threads to move forward or backward. The wrap threads come from rotate apparatus installed on the roller matrix. The rotate apparatus is controlled individually to forward or reverse rotate, so that the attached wrap thread is able to be longer or shorter. As the wrap threads can be shortened during weaving process, the three-dimensional surface can be produced.

Abstract: A substrate processing apparatus includes a vacuum chamber with upper and lower electrodes and a processing zone for processing a substrate using plasma. The upper electrode includes a surface that is substantially parallel to a surface of the substrate when the substrate is positioned in the chamber. The apparatus includes at least one magnetic field source configured to generate one or more active magnetic fields through the processing zone, and a controller coupled to the at least one magnetic field source and the upper electrode. The controller is configured to apply RF power between the upper and lower electrodes to generate the plasma using a process gas. The controller controls the current through the at least one magnetic field source during the processing of the substrate, where the current is based on a target value corresponding to at least one characteristic of the one or more active magnetic fields.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.