Patents by Inventor Chen Lin

Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240177365
    Abstract: The present disclosure provides an effect application previewing method, an apparatus, a device and a storage medium. The method includes: taking, in response to a preview trigger operation for a target effect style, a position of a pointer on a video track as a start point, to generate a virtual video frame for the target effect style; synchronously playing the virtual video frame and at least one video clip corresponding to the virtual video frame on the video track based on a timeline, to preview an effect of the target effect style applied to the at least one video clip.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Zhaoqin LIN, Pingfei Fu, Yan Zeng, Qifan Zheng, Chen Zhao
  • Publication number: 20240179512
    Abstract: A method for of wireless communication, by a multi-subscription user equipment (UE) includes selecting a first subscription to receive a positioning system information broadcast (posSIB) based on a first subscription state and a second subscription state. The method also includes receiving the posSIB via the first subscription. The UE may switch from the first subscription to a second subscription to receive a subsequent posSIB, in response to the second subscription state changing and/or the first subscription state changing. The state switching may be between connected mode and inactive/idle mode, or between voice service and data service.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Kuo-Chun LEE, Qingxin CHEN, Arvind Vardarajan SANTHANAM, Reza SHAHIDI, Shanshan WANG, Liangchi HSU, Rishav REJ, Ie-Hong LIN, Karthik VENKATRAM, Subashini KRISHNAMURTHY, Sudeep JAIN, Amit JAIN, Tom CHIN
  • Publication number: 20240179388
    Abstract: This application discloses a camera module and an electronic device. The camera module includes a photosensitive chip, a first lens barrel, a first lens, a rotating assembly, an elastic member, and a drive mechanism. The first lens barrel is provided with the first lens that is disposed opposite the photosensitive chip. The rotating assembly fits around the first lens barrel, and is connected to the rotating assembly via a first fitting convex portion and a first spiral guide slot. The rotating assembly includes a body member and a transmission member that are disposed separately. A first end of the elastic member is connected to the body member, and a second end of the elastic member is connected to the transmission member. The drive mechanism is connected to the transmission member, and the drive mechanism drives, via the transmission member, the elastic member, and the body member in turn.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Guanglong CHEN, Dongcun Cheng, Haibo Que, Jian Tang Lin
  • Publication number: 20240174894
    Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 30, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang, Yi-Ping Chen
  • Patent number: 11997855
    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Mauricio Manfrini, Han-Jong Chia
  • Patent number: 11994736
    Abstract: An imaging lens assembly has an optical axis and includes an annular structure located on an object side of the imaging lens assembly and surrounds the optical axis. The annular structure is located on an object side of the imaging lens assembly, surrounds the optical axis, and includes a first through hole, a second through hole, a first frustum surface, a second frustum surface and a third frustum surface. The first through hole is disposed on an object side of the annular structure, and the second through hole is disposed on an image side of the first through hole. The first frustum surface is disposed on the image side of the first through hole. The second frustum surface is disposed on an object side of the second through hole. The third frustum surface is disposed on an image side of the second through hole.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 28, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Chen Lai, Ming-Ta Chou, Cheng-Feng Lin, Ming-Shun Chang
  • Patent number: 11994809
    Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe positioned above the semiconductor manufacturing equipment and having a top surface and a bottom surface extending parallel to the top surface; a first branch pipe including an upstream end coupled to a source of a gas mixture and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including an upstream end and a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Patent number: 11994450
    Abstract: A field surveying and regulating method applied on at least one monitoring electronic device enables at least one manager to add at least one project and at least one specific location (spot) for obtaining soil samples and to edit the at least one project and the at least one spot on an online map. The method allows the manager to assign at least one soil drill and at least one drill operator for each project and each spot. The method enables the manager to view information as to position of each soil drill, depth for sampling by each soil drill, sampling time spent, actual work done by each soil drill, and photos of work by each soil drill in sampling. A related field surveying and regulating system is also disclosed.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: May 28, 2024
    Assignee: FOXSEMICON INTEGRATED TECHNOLOGY, INC.
    Inventors: Ching-Wen Lin, Wei-Chen Su
  • Publication number: 20240170204
    Abstract: A magnetic device includes a base plate, a cover plate, a first winding column, a second winding column, a primary winding, a secondary winding and a supporting column. The base plate, having a first concave portion, is opposite to the cover plate. The first winding column and the second winding column are disposed between the bottom plate and the cover plate, respectively. The primary winding and the secondary winding are wound around the first winding column and the second winding column. The supporting column is disposed between the base plate and the cover plate. A first concave portion concaves from a first side of the base plate towards the first winding column and the second winding column along multiple directions. The primary winding and the secondary winding are wound and stacking along an extension direction of the first winding column and the second winding column.
    Type: Application
    Filed: July 20, 2023
    Publication date: May 23, 2024
    Inventors: Chen CHEN, De-Jia LU, Kai-De CHEN, Yong-Long SYU, Chao-Lin CHUNG
  • Publication number: 20240172380
    Abstract: The present invention provides a display panel and a mobile terminal, including a panel layer including, but not limited to, a first portion, a second portion, and a curved third portion connected therebetween; a protective layer on the third portion; a first support layer on a side of the panel layer away from the protective layer and disposed opposite to the first portion; and a cover layer on the first portion and including an edge as an ink layer; the protective layer has a minimum thickness on a side close to the first portion and between a boundary of the first portion and an inner boundary of the ink layer.
    Type: Application
    Filed: March 14, 2022
    Publication date: May 23, 2024
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Feiming Lin, Chen Zhao, Kuihua You, Xiaowen Huang
  • Patent number: 11989966
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 21, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Chih-Hsien Chen
  • Patent number: 11989373
    Abstract: A circuit to cancel the effect of parasitic capacitances (“initial signals”) in calculations as to precise touch locations on a touch display screen (signal compensation circuit) includes first and second compensation circuits connected to a charge-discharge node. The first compensation circuit receives initial signals, generates first charging currents to charge, and first discharging currents to discharge, the charging-discharging node. The second compensation circuit generates second charging currents to charge, and second discharging currents to discharge, the charging-discharging node. Values of the first charging currents, the second charging currents, the first discharging currents, and the second discharging currents are of different magnitudes and are applied in order to amount to a more precise match for the exact compensation value required.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: May 21, 2024
    Assignee: JADARD TECHNOLOGY INC.
    Inventors: Feng-Wei Lin, Yu-Chieh Hsu, Long Chen
  • Patent number: 11990418
    Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hua Wang, Po-Chen Lai, Ping-Tai Chen, Che-Chia Yang, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11986869
    Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Chen Ho, Chih Ping Liao, Ker-hsun Liao, Chi-Hsun Lin
  • Patent number: 11991886
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Bo-Feng Young, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20240161787
    Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.
    Type: Application
    Filed: August 10, 2023
    Publication date: May 16, 2024
    Inventors: Chien-Chen Lin, Wei Min Chan
  • Publication number: 20240164109
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 16, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240162267
    Abstract: The present invention discloses a microminiature image acquisition and processing system package structure and a preparation method thereof. This structure includes optical coated glass, a CMOS chip, a wafer Re-Distribution Layer and a molding layer, the first surface of the CMOS chip is provided with a photosensitive and microlens region and a metal bonding pad, and a through-silicon via is etched in a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface; the wafer Re-Distribution Layer covers the second surface of the CMOS chip and extends to the through-silicon via. The structure and the method of the present invention are integrated with wafer-level package and SIP integrated package technologies to achieve single package of the whole device, thereby greatly reducing the system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference capability.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Applicant: JCET GROUP CO., LTD.
    Inventors: Jianyong Wu, Yaojian Lin, Danfeng Yang, Chen Xu, Wei Yan
  • Publication number: 20240162359
    Abstract: A backsheet of a solar cell module including a substrate, a first protection layer, and a second protection layer is provided. The substrate includes a first surface and a second surface opposite to each other. The first protection layer is disposed on the first surface of the substrate. The second protection layer is disposed on the second surface of the substrate, wherein the first protection layer and the second protection layer include a silicone layer. At least one of the first protection layer and the second protection layer includes diffusion particles, wherein the diffusion particles include zinc oxide, titanium dioxide modified with silicon dioxide, or a combination thereof. A thickness of the first protection layer and a thickness of the second protection layer are respectively 10 ?m to 30 ?m. A solar cell module including the backsheet is also provided.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 16, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Kang Peng, Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang
  • Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin