Patents by Inventor Chen-Ming Huang

Chen-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170263454
    Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 14, 2017
    Inventors: Kuan-Hsien Li, Rai-Min Huang, I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9748144
    Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang, Ren-Peng Huang, Ching-Fu Lin
  • Patent number: 9718164
    Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
  • Publication number: 20170207129
    Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 20, 2017
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20170154823
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 1, 2017
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9653402
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20170092643
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9608062
    Abstract: The present invention provides a semiconductor structure including a fin structure formed on a substrate, and an isolation structure formed in the fin structure. The isolation structure includes a trench, and a first dielectric layer disposed in the trench wherein the first dielectric layer includes a body portion in the bottom, a protruding portion in the top with a top surface, and a shoulder portion connecting the body portion and the protruding portion. The protruding portion has a smaller width than the body portion. The semiconductor structure further includes a second dielectric layer covering a top corner of the trench and sandwiched between the protruding portion, the shoulder portion of the first dielectric layer and the upper sidewall of the trench.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9607985
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20170047244
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20170040435
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Application
    Filed: August 30, 2015
    Publication date: February 9, 2017
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Publication number: 20170012000
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.
    Type: Application
    Filed: September 3, 2015
    Publication date: January 12, 2017
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9524909
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20160358930
    Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Chia-Ta Hsieh, Chi-Wei Ho, Kao-Chao Lin, Josh Lin, Nai-Chao Su, Shih-Jung Tu, Po-Kai Hsu, Shih-Ching Lee, Chen-Ming Huang
  • Publication number: 20160354328
    Abstract: Provided is a method for preparation of a sustained released pharmaceutical composition, wherein an active ingredient and a cellulose derivative dissolved in a lower alkyl alcohol solvent are processed with granulation such that the PEO does not need to be processed with granulation or sizing to achieve uniform drug distribution. Besides, the specific range of the viscosity of the cellulose derivate provides better uniformity to the sustained release pharmaceutical composition derived from the above preparation method.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 8, 2016
    Applicant: ANXO PHARMACEUTICAL CO., LTD.
    Inventors: Chen-Ming HUANG, Li-Chuan CHUANG, Chih-Hung LI
  • Patent number: 9502280
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Patent number: 9484263
    Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Li-Wei Feng, Shih-Hung Tsai, Jyh-Shyang Jenq, Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang
  • Patent number: 9466691
    Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Rai-Min Huang, Tong-Jyun Huang, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20160293491
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 6, 2016
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20160276429
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench. The spacer layer is disposed on sidewalls of the trench. The dummy gate structure is disposed across the trench and includes a portion thereof disposed in the trench.
    Type: Application
    Filed: April 13, 2015
    Publication date: September 22, 2016
    Inventors: I-Ming Tseng, Wen-An Liang, Rai-Min Huang, Chen-Ming Huang, Tong-Jyun Huang, Kuan-Hsien Li