Abstract: A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.

Abstract: An automatic memory characterization system for determining timing characteristics associated with each of a plurality of circuit instances of a memory compiler circuit design includes: an automatic circuit reduction tool for receiving a circuit netlist extracted from layout data defining a circuit instance of the memory compiler, and for generating a critical path netlist; a memory storage unit for storing a timing parameter database including a script file having memory characterization instructions, and at least one specification file associated with one of the timing characteristics to be characterized for the circuit instance, the specification file having a plurality of input signal parameters defining a plurality of input signals to be applied to selected input nodes of the circuit instance, and a plurality of output loading parameters defining a plurality of output loads to be applied to selected output nodes of the circuit instance; a stimulus generator responsive to the input signal parameters and o