Abstract: The present invention relates to a memory interlace-checking method and, in particular, to a test method that can effectively detect the weakening of memory. This test method is different from the conventional continuous address testing style. It is an interlacing address test method that comprises a main step and a data checking step. The main step provides main data to perform command actions on local addresses in memory. This will weaken other portions in the memory that are not trigged by commands because of the electromagnetic interference (EMI) induced by memory operations. Afterwards, in the data checking step, the yet to be triggered portion will be checked in a complementary way in order to accurately detect weakened memory.

Abstract: A method of testing memory using continuous, varying data. More specifically, a method for testing whether a memory is weakened or damaged by continuously inputting and outputting varying data through the data I/O pins of the memory. At least a 75% data variation ratio on the test data is maintained to ensure high accuracy in detecting a weakened or damaged memory.

Abstract: A method for testing memories has steps of providing seamless data to data input/output pins and providing seamless control commands to each bank at each clock cycle, when the memories receive the seamless data and control commands, and the data input/output pins of memories receive heavy loads status. For SDRAM and DDR-DRAM, control commands and data are seamlessly inputted/outputted at each clock cycle. For RDRAM, control commands are inputted at each “command packet”, whereby data are inputted/outputted at each “data packet” and memories are in the heavy loading status. By providing heavy loading to control pins and data input/output pins of memories, it is easy to detect weakened memories.

Abstract: A method of testing memory using continuous, varying data. More specifically, a method for testing whether a memory is weakened or damaged by continuously inputting and outputting varying data through the data I/O pins of the memory. At least a 75% data variation ratio on the test data is maintained to ensure high accuracy in detecting a weakened or damaged memory.

Abstract: A method for testing memories has steps of providing seamless data to data input/output pins and providing seamless control commands to each bank at each clock cycle, when the memories receive the seamless data and control commands, and the data input/output pins of memories receive heavy loads status. For SDRAM and DDR-DRAM, control commands and data are seamlessly inputted/outputted at each clock cycle. For RDRAM, control commands are inputted at each “command packet”, whereby data are inputted/outputted at each “data packet” and memories are in the heavy loading status. By providing heavy loading to control pins and data input/output pins of memories, it is easy to detect weakened memories.

Abstract: The present invention relates to a memory interlace-checking method and, in particular, to a test method that can effectively detect the weakening of memory. This test method is different from the conventional continuous address testing style. It is an interlacing address test method that comprises a main step and a data checking step. The main step provides main data to perform command actions on local addresses in memory. This will weaken other portions in the memory that are not trigged by commands because of the electromagnetic interference (EMI) induced by memory operations. Afterwards, in the data checking step, the yet to be triggered portion will be checked in a complementary way in order to accurately detect weakened memory.

Abstract: This invention discloses a dual damascene structure supported on a semiconductor substrate. The dual damascene structure includes an etch-differentiating layer disposed above a top surface of the substrate. The dual damascene structure further includes a trench disposed on a top portion in the etch-differentiating layer. The dual damascene structure further includes an etched via disposed in the trench penetrating the etch differentiating layer therethrough above a non-etch-damaged portion of the top surface of the substrate.

Abstract: This invention discloses a method of planarizing a top surface with variations of profile heights above a substrate of a semiconductor chip. The method includes a step producing a polish-differentiating surface which has polishing rates proportional to the variations of the profile heights of the polish-differentiating surface above the substrate provided for performing a planarization process by applying a polishing process thereon. With the polishing differentiating surface the dishing effects of the semiconductor chip is substantially reduced when a one-time chemical mechanical polishing (CMP) process is applied for semiconductor chip planarization.