Abstract: A semiconductor device includes a substrate; a fin structure disposed over the substrate; a gate structure disposed over the substrate, wherein an extension direction of the fin structure intersects an extension direction of the gate structure; and a first well disposed under the gate structure, corresponding to an emitter region of the semiconductor device, and having a first conductivity type, wherein the first well is adjacent to a well block layer, and the well block layer is disposed under the gate structure in the emitter region; wherein the well block layer has a first doping concentration of a well implant, the first well has a second doping concentration of the well implant, and the first doping concentration is less than the second doping concentration.

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack with a metal gate layer and a spacer layer disposed on a sidewall of the gate stack. In some embodiments, the method further includes performing an etch-back process to the metal gate layer to form an opening over the gate stack. In various examples, the method further includes performing a plasma treatment process to modify a profile of the opening. In some cases, the method further includes forming a HM layer over the metal gate layer and within the opening having the modified profile.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.

Abstract: Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; performing an in-situ doping process to form a first fluorine-containing layer on the buffer layer; forming a barrier layer on the first fluorine-containing layer; forming a second fluorine-containing layer on the barrier layer; forming a gate electrode on the second fluorine-containing layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

Abstract: A bipolar junction transistor includes: an emitter region; a base region; and a collector region, wherein each of the emitter region, the base region, and the collector region comprises fin-shaped structures. Preferably, the emitter region, the base region, and the collector region are disposed along a first direction and the fin-shaped structures are disposed along a second direction, in which the first direction is orthogonal to the second direction.

Abstract: A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.

Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Abstract: A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.

Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

Abstract: A bipolar junction transistor preferably includes: an emitter region; a base region; and a collector region, in which an edge of the emitter region is aligned with an edge of the base region. Preferably, an edge of the base region is aligned with an edge of the collector region, the edge of the emitter region is aligned with the edges of the base region and the collector region, and the widths of the emitter region, the base region, and the collector region are equivalent. According to a top view of the bipolar junction transistor, each of the base region and the collector region includes a rectangle.

Abstract: A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

Abstract: A bipolar junction transistor includes: an emitter region; a base region; and a collector region, wherein each of the emitter region, the base region, and the collector region comprises fin-shaped structures. Preferably, the emitter region, the base region, and the collector region are disposed along a first direction and the fin-shaped structures are disposed along a second direction, in which the first direction is orthogonal to the second direction.

Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.