Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.

Abstract: In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a ? baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The ? baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.

Abstract: In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a ? baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The ? baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.

Abstract: A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.

Abstract: A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: An apparatus of sequentially decoding CCK codes includes a series of received signal registers used to respectively temporarily save the received signals, a phase selector used to select one numeral from 1, ?1, j or ?j respectively for CCK code of each chip to multiple with the signal register, a series of adders used to sequentially complete adding operation, a series of sequential operation registers used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders, and a comparing device used to select a maximal value from those saved in the operation registers. The comparing device includes a comparator and a maximum register. According to the invention, the data processing speeds up while the hardware complexity is reduced.

Abstract: A system and method for channel estimation in a wireless local area network. A corresponding channel estimation method includes the steps of: receiving a preamble message and despreading the preamble message into several symbol signals, each symbol signal containing several discrete signals; determining for each symbol signal a peak sign assignment; establishing several data windows for the symbol signals at the starting points of the discrete signals; multiplying the discrete value of each discrete signal of each data window by the corresponding peak sign assignment and accumulating the product in the first data frame; repeating the above steps for the next discrete signal and accumulating them in the second data frame, . . . , the Nth data frame; computing the accumulated value in the data frames and obtaining the data frame with the maximum value; estimating a channel signal from the previously determined data frame.

Abstract: An apparatus of sequentially decoding CCK codes includes a series of received signal registers used to respectively temporarily save the received signals, a phase selector used to select one numeral from 1, ?1, j or ?j respectively for CCK code of each chip to multiple with the signal register, a series of adders used to sequentially complete adding operation, a series of sequential operation registers used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders, and a comparing device used to select a maximal value from those saved in the operation registers. The comparing device includes a comparator and a maximum register. According to the invention, the data processing speeds up while the hardware complexity is reduced.

Abstract: A system and method for channel estimation in a wireless local area network. A corresponding channel estimation method includes the steps of: receiving a preamble message and dispreading the preamble message into several symbol signals, each symbol signal containing several discrete signals; determining for each symbol signal a peak sign assignment; establishing several data windows for the symbol signals at the starting points of the discrete signals; multiplying the discrete value of each discrete signal of each data window by the corresponding peak sign assignment and accumulating the product in the first data frame; repeating the above steps for the next discrete signal and accumulating them in the second data frame, . . . , the Nth data frame; computing the accumulated value in the data frames and obtaining the data frame with the maximum value; estimating a channel signal from the previously determined data frame.