Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores a custom extreme memory profile (XMP). When the processor executes the BIOS, so that the computer device displays a user interface (UI), the BIOS displays multiple default XMPs stored in the memory module and the custom XMP through the UI. The BIOS stores one of the default XMPs and the custom XMP to the memory module according to a selecting result of the one of the default XMPs and the custom XMP displayed on the UI.

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Abstract: The present invention relates to the mRNA vaccine of coronavirus spike protein with deletion of glycosites in the receptor binding domain (RBD), the subunit 1 (S1) domain, or the subunit 2 (S2) domain, or a combination thereof. The vaccine elicits broadly protective immune responses coronavirus and variants thereof.

Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of first dielectric layers, a plurality of metal layers of Ag or its alloy and a plurality of second dielectric layers are formed over the substrate. The plurality of first dielectric layers and the plurality of metal layers are alternately formed over the substrate. The plurality of second dielectric layers are formed on one side away from the substrate of the plurality of metal layers and located between the plurality of metal layers and the plurality of first dielectric layers. An optical element fabricated by the method is also provided.

Abstract: A display device includes a substrate, gate lines, a driving circuit, and auxiliary gate lines. The substrate has a display area. The gate lines are disposed on the display area, and are in parallel with a first edge of the display area. The gate lines include a first gate line which is farthest from the first edge. The driving circuit is disposed adjacent to the first edge. The auxiliary gate lines substantially perpendicular to the gate lines are connected to the gate lines, and are in parallel with a second edge of the display area. The auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is configured to connect the first gate line to the driving circuit. The at least one auxiliary gate line is disposed between the second edge and the first auxiliary gate line.

Abstract: A display device includes a substrate, gate lines, a driving circuit, and auxiliary gate lines. The substrate has a display area. The gate lines are disposed on the display area, and are in parallel with a first edge of the display area. The gate lines include a first gate line which is farthest from the first edge. The driving circuit is disposed adjacent to the first edge. The auxiliary gate lines substantially perpendicular to the gate lines are connected to the gate lines, and are in parallel with a second edge of the display area. The auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is configured to connect the first gate line to the driving circuit. The at least one auxiliary gate line is disposed between the second edge and the first auxiliary gate line.

Abstract: A display panel includes a first substrate, a second substrate, a display medium layer, pixel units, and a light-shielding conductive pattern layer. The first substrate has a first inner surface and a first outer surface, and the first outer surface serves as a display surface of the display panel. The second substrate is disposed opposite to the first substrate and has a second inner surface and a second outer surface. The display medium layer is disposed between the first inner surface and the second inner surface. The pixel units are disposed between the display medium layer and the first inner surface, and at least one of the pixel units includes an active element. The light-shielding conductive pattern layer is disposed between the display medium layer and the second inner surface, at least partially overlaps the active element in a vertical projection direction, and includes a first patterned light-shielding conductive layer and a first patterned low-reflection layer.

Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of first dielectric layers, a plurality of metal layers of Ag or its alloy and a plurality of second dielectric layers are formed over the substrate. The plurality of first dielectric layers and the plurality of metal layers are alternately formed over the substrate. The plurality of second dielectric layers are formed on one side away from the substrate of the plurality of metal layers and located between the plurality of metal layers and the plurality of first dielectric layers. An optical element fabricated by the method is also provided.

Abstract: A display panel includes a first substrate, a second substrate, a display medium layer, pixel units, and a light-shielding conductive pattern layer. The first substrate has a first inner surface and a first outer surface, and the first outer surface serves as a display surface of the display panel. The second substrate is disposed opposite to the first substrate and has a second inner surface and a second outer surface. The display medium layer is disposed between the first inner surface and the second inner surface. The pixel units are disposed between the display medium layer and the first inner surface, and at least one of the pixel units includes an active element. The light-shielding conductive pattern layer is disposed between the display medium layer and the second inner surface, at least partially overlaps the active element in a vertical projection direction, and includes a first patterned light-shielding conductive layer and a first patterned low-reflection layer.

Abstract: A liquid crystal pixel circuit and a driving method thereof are provided. The liquid crystal pixel circuit has a main pixel, a sub pixel and a charge sharing switch. The charge sharing switch is electrically coupled between the main pixel and the sub pixel. The main pixel, the sub pixel and the charge sharing switch are controlled by the same gate line. The provided driving method is used for driving the liquid-crystal pixel circuit mentioned above.

Abstract: A liquid crystal pixel circuit and a driving method thereof are provided. The liquid crystal pixel circuit has a main pixel, a sub pixel and a charge sharing switch. The charge sharing switch is electrically coupled between the main pixel and the sub pixel. The main pixel, the sub pixel and the charge sharing switch are controlled by the same gate line. The provided driving method is used for driving the liquid-crystal pixel circuit mentioned above.

Abstract: A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.

Abstract: A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.

Abstract: A thin film transistor (TFT) and a pixel structure having the TFT are provided. The TFT is configured on a substrate. Besides, the TFT includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers the gate and the substrate. The source is configured on a portion of the gate insulation layer. The channel layer is configured on the gate insulation layer and covers a portion of the source located above the gate. The drain is configured on and electrically connected to the channel layer.