Patents by Inventor Chen-Yong Cher

Chen-Yong Cher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MANAGING HIGH PERFORMANCE STORAGE SYSTEMS WITH HYBRID STORAGE TECHNOLOGIES
    Publication number: 20230049904
    Abstract: There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 16, 2023
    Inventors: Ashish Jagmohan, Chen-Yong Cher, Michele Martino Franceschini
  • Managing high performance storage systems with hybrid storage technologies
    Patent number: 11537290
    Abstract: There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: December 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Michele M. Franceschini, Ashish Jagmohan
  • Network resiliency through memory health monitoring and proactive management
    Patent number: 11121951
    Abstract: A method for managing a network queue memory includes receiving sensor information about the network queue memory, predicting a memory failure in the network queue memory based on the sensor information, and outputting a notification through a plurality of nodes forming a network and using the network queue memory, the notification configuring communications between the nodes.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
  • Chip transient temperature predictor
    Patent number: 10948955
    Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen-Yong Cher, Haifeng Qian
  • Reliability-aware runtime optimal processor configuration
    Patent number: 10896146
    Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik V. Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose, Nandhini Chandramoorthy, Chen-Yong Cher
  • Dynamic predictor of semiconductor lifetime limits
    Patent number: 10746785
    Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen-Yong Cher, Keith A. Jenkins, Barry P. Linder
  • RELIABILITY-AWARE RUNTIME OPTIMAL PROCESSOR CONFIGURATION
    Publication number: 20200159691
    Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Karthik V. Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose, Nandhini Chandramoorthy, Chen-Yong Cher
  • Optimization of application workflow in mobile embedded devices
    Patent number: 10635490
    Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ramon Bertran Monfort, Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Hans M. Jacobson, William J. Song, Karthik V. Swaminathan, Augusto J. Vega, Liang Wang
  • Checkpoint triggering in a computer system
    Patent number: 10585753
    Abstract: According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation. The state data of the checkpoint is restored from a memory responsive to detecting an error condition at the processing node. Execution of the task is restarted in the processing node based on the state data restored from the memory.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chen-Yong Cher
  • CHIP TRANSIENT TEMPERATURE PREDICTOR
    Publication number: 20200057479
    Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 20, 2020
    Applicant: International Business Machines Corporation
    Inventors: CHEN-YONG CHER, HAIFENG QIAN
  • Checkpointing using compute node health information
    Patent number: 10545839
    Abstract: A method is disclosed, as well as an associated apparatus and computer program product, for checkpointing using a plurality of communicatively coupled compute nodes. The method comprises acquiring health information for a first node of the plurality of compute nodes, and determining a first failure probability for the first node using the health information. The first failure probability corresponds to a predetermined time interval. The method further comprises selecting a second node of the plurality of compute nodes as a partner node for the first node. The second node has a second failure probability for the time interval. A composite failure probability of the first node and the second node is less than the first failure probability. The method further comprises copying checkpoint information from the first node to the partner node.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carlos Henrique Andrade Costa, Yoonho Park, Chen-Yong Cher, Bryan Rosenburg, Kyung Ryu
  • Chip transient temperature predictor
    Patent number: 10528097
    Abstract: An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen-Yong Cher, Haifeng Qian
  • Autonomic supply voltage compensation for degradation of circuits over circuit lifetime
    Patent number: 10365702
    Abstract: Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Pierce I Chuang, Keith A Jenkins, Barry Linder
  • CHECKPOINTING USING COMPUTE NODE HEALTH INFORMATION
    Publication number: 20190196920
    Abstract: A method is disclosed, as well as an associated apparatus and computer program product, for checkpointing using a plurality of communicatively coupled compute nodes. The method comprises acquiring health information for a first node of the plurality of compute nodes, and determining a first failure probability for the first node using the health information. The first failure probability corresponds to a predetermined time interval. The method further comprises selecting a second node of the plurality of compute nodes as a partner node for the first node. The second node has a second failure probability for the time interval. A composite failure probability of the first node and the second node is less than the first failure probability. The method further comprises copying checkpoint information from the first node to the partner node.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Carlos Henrique ANDRADE COSTA, Yoonho PARK, Chen-Yong CHER, Bryan ROSENBURG, Kyung RYU
  • Method and apparatus for selective and power-aware memory error protection and memory management
    Patent number: 10141955
    Abstract: A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.
    Type: Grant
    Filed: April 11, 2015
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
  • CHECKPOINT TRIGGERING IN A COMPUTER SYSTEM
    Publication number: 20180329779
    Abstract: According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation. The state data of the checkpoint is restored from a memory responsive to detecting an error condition at the processing node. Execution of the task is restarted in the processing node based on the state data restored from the memory.
    Type: Application
    Filed: July 12, 2018
    Publication date: November 15, 2018
    Inventor: Chen-Yong Cher
  • Autonomic Supply Voltage Compensation for Degradation of Circuits over Circuit Lifetime
    Publication number: 20180292879
    Abstract: Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Chen-Yong Cher, Pierce I Chuang, Keith A. Jenkins, Barry Linder
  • Checkpoint triggering in a computer system
    Patent number: 10089181
    Abstract: According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node and determining whether it is time to read a monitor associated with a metric of the task. The monitor is read to determine a value of the metric based on determining that it is time to read the monitor. A threshold for triggering creation of the checkpoint is determined based on the metric. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the value of the metric has crossed the threshold and the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chen-Yong Cher
  • Methods, apparatus and system for selective duplication of subtasks
    Patent number: 10073739
    Abstract: A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu