Patents by Inventor Chen-Yuan Kao
Chen-Yuan Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087961Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11901426Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.Type: GrantFiled: December 16, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11855154Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.Type: GrantFiled: August 3, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
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Patent number: 11820968Abstract: Applications in transfusion medicine requiring platelets, and hematopoietic stem-cell transplantations require either platelets or enhancement of in vivo platelet biogenesis. Gene therapy applications of hematopoietic stem and progenitor cells (HSPCs) require effective and specific modification of HSPCs by DNA, RNA or other biological molecules. Here we disclose methods for the generation, and modification of megakaryocytic microparticles (MkMPs), proplatelets, preplatelets, platelet-like particles and megakaryocyte extracellular vesicles, that can be used in the aforementioned transfusion and transplantation medicine applications and in gene therapy applications involving hematopoietic stem cells.Type: GrantFiled: December 11, 2019Date of Patent: November 21, 2023Inventors: Eleftherios Papoutsakis, Chen-Yuan Kao, Jinlin Jiang
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Publication number: 20230369500Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
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Publication number: 20230343712Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Publication number: 20230342536Abstract: A capture IR drop analyzer and an analyzing method thereof are provided. The capture IR drop analyzing method includes: receiving circuit layout information and package model information of a circuit; analyzing a plurality of circuit blocks respectively corresponding to a plurality of bump current sources according to the circuit layout information and the package model information; calculating at least one critical circuit block according to each of the bump current sources and a current demand value of each of the corresponding circuit blocks; and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.Type: ApplicationFiled: June 20, 2022Publication date: October 26, 2023Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Min-Hsiu Tsai
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Patent number: 11777035Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.Type: GrantFiled: June 27, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
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Publication number: 20230290842Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.Type: ApplicationFiled: May 15, 2023Publication date: September 14, 2023Inventors: Cheng-Wei Chang, Hong-Ming Wu, Chen-Yuan Kao, Li-Hsiang Chao, Yi-Ying Liu
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Publication number: 20230215807Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: January 9, 2023Publication date: July 6, 2023Inventors: Wen-Jiun LIU, Chen-Yuan KAO, Hung-Wen SU, Ming-Hsing TSAI, Syun-Ming JANG
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Patent number: 11652149Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.Type: GrantFiled: December 4, 2020Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Wei Chang, Hong-Ming Wu, Chen-Yuan Kao, Li-Hsiang Chao, Yi-Ying Liu
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Publication number: 20230121981Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11630479Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.Type: GrantFiled: July 7, 2020Date of Patent: April 18, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tse-Wei Wu, Chen-Yuan Kao, Min-Hsiu Tsai
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Publication number: 20230029508Abstract: Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.Type: ApplicationFiled: May 5, 2022Publication date: February 2, 2023Inventors: Yu-Syuan TSAI, Chen-Yuan KAO, Chia-Han LAI, Hong-Ming WU, Yu-Chan TSAI, Chun-Hsien HUANG, Ken-Yu CHANG
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Patent number: 11552018Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: May 3, 2021Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Patent number: 11535950Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: GrantFiled: November 13, 2019Date of Patent: December 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 11532717Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.Type: GrantFiled: February 15, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11532561Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: GrantFiled: August 4, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Publication number: 20220372441Abstract: The present invention relates to a method for inducing megakaryocytic differentiation of hematopoietic stem/progenitor cells (HSPCs). The method comprises transferring into the HSPCs an effective amount of small RNAs. The HSPCs may differentiate into megakaryocytes in the absence of thrombopoietin (TPO) and/or without using megakaryocytic microparticles (MkMPs). The small RNAs may be micro RNAs (miRs) selected from the group consisting of miR-486, miR-22, miR-191, miR-181, miR-378, miR-26, let-7, miR-92, miR-126, miR-92, miR-21, miR-146, miR-181, and combinations thereof. For example, the small RNAs are miR-486 and miR-22. The small RNAs may be synthetic or isolated from cells. Also provided is a method for enhancing megakaryocytic differentiation of HSPCs cultured with megakaryocytic microparticles MkMPs in the presence of an effective amount of one or more exogenous small RNAs (e.g., miR-486).Type: ApplicationFiled: October 21, 2020Publication date: November 24, 2022Applicant: University of DelawareInventors: Eleftherios Papoutsakis, Chen-Yuan Kao, Jinlin Jiang