Patents by Inventor Chen-Yueh Kung
Chen-Yueh Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10573614Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.Type: GrantFiled: September 5, 2018Date of Patent: February 25, 2020Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 10459007Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: GrantFiled: December 17, 2018Date of Patent: October 29, 2019Assignee: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Publication number: 20190120875Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Applicant: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Patent number: 10204852Abstract: A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.Type: GrantFiled: February 3, 2017Date of Patent: February 12, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Yeh-Chi Hsu, Chen-Yueh Kung
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Patent number: 10184956Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: GrantFiled: May 21, 2018Date of Patent: January 22, 2019Assignee: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Publication number: 20190006302Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.Type: ApplicationFiled: September 5, 2018Publication date: January 3, 2019Applicant: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 10119995Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: GrantFiled: January 8, 2014Date of Patent: November 6, 2018Assignee: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Patent number: 10103115Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.Type: GrantFiled: October 16, 2013Date of Patent: October 16, 2018Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Publication number: 20180267084Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: ApplicationFiled: May 21, 2018Publication date: September 20, 2018Applicant: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Patent number: 10014246Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.Type: GrantFiled: October 3, 2016Date of Patent: July 3, 2018Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 10002839Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.Type: GrantFiled: June 29, 2017Date of Patent: June 19, 2018Assignee: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
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Publication number: 20180061790Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.Type: ApplicationFiled: June 29, 2017Publication date: March 1, 2018Applicant: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
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Publication number: 20180061789Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.Type: ApplicationFiled: June 29, 2017Publication date: March 1, 2018Applicant: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
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Patent number: 9905519Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.Type: GrantFiled: June 29, 2017Date of Patent: February 27, 2018Assignee: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
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Patent number: 9786588Abstract: The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces.Type: GrantFiled: September 21, 2015Date of Patent: October 10, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Chen-Yueh Kung, Hsin-I Chuang, Ting-You Wei
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Publication number: 20170148720Abstract: A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: Yeh-Chi HSU, Chen-Yueh KUNG
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Patent number: 9601425Abstract: The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.Type: GrantFiled: August 18, 2015Date of Patent: March 21, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Yeh-Chi Hsu, Chen-Yueh Kung
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Publication number: 20170025343Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.Type: ApplicationFiled: October 3, 2016Publication date: January 26, 2017Applicant: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 9532467Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.Type: GrantFiled: September 6, 2013Date of Patent: December 27, 2016Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 9497864Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.Type: GrantFiled: May 21, 2013Date of Patent: November 15, 2016Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung