Patents by Inventor Chenbo Liu

Chenbo Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with on-chip power profiling
    Patent number: 9696775
    Abstract: Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 4, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Tian Yan Pu, Chenbo Liu, Thuyen Le, Lars Melzer
  • INTEGRATED CIRCUIT WITH ON-CHIP POWER PROFILING
    Publication number: 20160259397
    Abstract: Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 8, 2016
    Inventors: Tian Yan Pu, Chenbo Liu, Thuyen Le, Lars Melzer